Couplings within memory devices and methods

Details Couplings within memory devices and methods Couplings within memory devices and methods

2006-04-18

2009-12-15

Luu, Pho M. (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S189020, C365S190000, C365S205000, C365S207000

Reexamination Certificate

active

07633786

ABSTRACT:
Methods and apparatus are provided. A memory device includes a first bit line selectively coupled to an input of a sensing device through a first multiplexer gate, and a second bit line selectively coupled to the input of the sensing device through a second multiplexer gate. The first bit line is formed at a first vertical layer and is coupled to a first source/drain region of the first multiplexer gate. The input of the sensing device is formed at a second vertical layer different than the first vertical layer and is coupled to a second source/drain region of the first multiplexer gate and a first source/drain region of the second multiplexer gate. The second bit line is formed at the first vertical layer and is coupled to a second source/drain region of the second multiplexer gate.

REFERENCES:
patent: 5280441 (1994-01-01), Wada et al.
patent: 6084820 (2000-07-01), Raszka
patent: 7095658 (2006-08-01), Cioaca

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