Static information storage and retrieval – Floating gate
Reexamination Certificate
2002-03-01
2003-08-05
Le, Thong Q. (Department: 2818)
Static information storage and retrieval
Floating gate
C365S185240, C365S185260
Reexamination Certificate
active
06603679
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a coupling coefficient measuring method and a coupling coefficient measuring apparatus for a semiconductor memory, and more specifically, it relates to a coupling coefficient measuring method and a coupling coefficient measuring apparatus for a nonvolatile semiconductor memory such as a flash memory.
2. Description of the Prior Art
A nonvolatile semiconductor memory such as an EPROM (erasable and programmable read only memory) or an EEPROM (electrically erasable and programmable read only memory) is recently watched with interest as a semiconductor memory capable of substituting for a hard disk and a floppy disk, which are magnetic memories.
A memory cell of an EPROM or an EEPROM stores carriers in a floating gate electrode for storing data in response to presence/absence of the carriers and reading data by detecting change of a threshold voltage responsive to presence/absence of the carriers. In particular, the EEPROM includes a flash EEPROM erasing data in the overall memory cell array or dividing the memory cell array into arbitrary blocks for erasing data in units of the blocks. The flash EEPROM is also referred to as a flash memory. The flash memory, capable of increasing the capacity, reducing the power consumption and increasing the speed and excellent in impact resistance, is used in various portable apparatuses. Each memory cell of the flash memory is formed by a single transistor, to advantageously enable easier integration as compared with an EEPROM.
In general, stacked gate and split gate memory cells are proposed for forming such a flash memory.
The stacked gate memory cell injects electrons stored in a channel of a semiconductor substrate into a floating gate electrode as hot electrons in a write operation of storing electrons in the floating gate electrode. At this time, a voltage of 10-odd V must be applied to a control gate electrode. In the stacked gate memory cell, a Fowler-Nordheim tunnel current (hereinafter referred to as an F-N tunnel current) is fed from a source or drain region to the floating gate electrode in an erase operation of extracting electrons stored in the floating gate electrode. At this time, a voltage of 10-odd V must be applied between the source or drain region and the floating gate electrode.
The split gate memory cell injects electrons stored in a channel of a semiconductor substrate into a floating gate electrode as hot electrons in a write operation of storing electrons in the floating gate electrode. At this time, a voltage of 10-odd V must be applied to a drain region. In the split gate memory cell, an F-N tunnel current is fed from a control gate electrode to the floating gate electrode in an erase operation of extracting electrons stored in the floating gate electrode. At this time, a voltage of 10-odd V must be applied to the control gate electrode.
Thus, each of the conventional stacked gate and split gate memory cells utilizes hot electrons for injecting electrons into the floating gate electrode in the write operation while utilizing the F-N tunnel current for extracting the electrons stored in the floating gate electrode in the write operation.
In the flash memory, the coupling coefficient between the floating gate electrode and the source region and that between the floating gate electrode and the control gate electrode are important parameters. These coupling coefficients decide controllability in erasing, writing and reading.
In order to control the potential of a floating gate electrode with the minimum voltage (power) in a general split gate flash memory controlling the potential of the floating gate electrode by electrostatic coupling from a source region, the coupling ratio between the source region (source diffusion layer) and the floating gate electrode must be sufficiently large. In this case, it is important to optimize cell creation conditions by correctly measuring the coupling ratio in the stage of development.
In general, the coupling ratio between the floating gate electrode and the control gate electrode is measured through a non-floating gate electrode (NFG) having a test structure. More specifically, a voltage is directly applied to the non-floating gate electrode whose voltage can be controlled by an external power source for measuring a subthreshold current, while the voltage of a control gate electrode is increased in an actual cell for measuring a subthreshold current. The ratio of inclinations (S values) of these subthreshold currents is calculated thereby measuring the coupling coefficient between the floating gate electrode and the control gate electrode. As to the split gate flash memory related to the present invention, it is recognized that the magnitude of coupling between elements other than “a source and a control gate” and a floating gate is extremely small. Therefore, the coupling ratio between the floating gate electrode and the source region important in writing is calculated by subtracting the coupling coefficient between the floating gate electrode and the control gate electrode from 1.
In the aforementioned method of measuring the coupling coefficient with the test structure including the non-floating gate electrode, however, it is difficult to independently form an external wire connected to the non-floating gate electrode following refinement of the cell, disadvantageously leading to difficulty in formation of the test structure. Following refinement of the cell, further, the shape of the actual cell may differ from that of the cell of the test structure due to the external wire for the non-floating gate electrode. In this case, the measured value of the subthreshold current in the test structure may differ from that in the actual cell. Consequently, it is difficult to correctly measure the coupling coefficient.
Even if the test structure can be created, there is a possibility of extracting a false value unless measuring conditions are optimized. Thus, the measuring conditions must be carefully set.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a coupling coefficient measuring method for a semiconductor memory capable of directly measuring a coupling coefficient in an actual cell without employing a specific test structure including a non-floating gate structure or the like.
Another object of the present invention is to provide a coupling coefficient measuring method for a semiconductor memory capable of correctly measuring a coupling coefficient.
Still another object of the present invention is to provide a coupling coefficient measuring apparatus for a semiconductor memory capable of directly measuring a coupling coefficient in an actual cell without employing a specific test structure including a non-floating gate structure or the like.
According to a first aspect of the present invention, a coupling coefficient measuring method for a semiconductor memory having a first gate electrode and a source region coupled at a prescribed electrostatic coupling ratio comprises steps of increasing a source voltage while setting a drain voltage to a first drain voltage defining a reference value for measuring a first subthreshold current flowing through a first transistor having the first gate electrode as a gate, increasing the source voltage while setting the drain voltage to a second drain voltage higher by a prescribed value than the first drain voltage for measuring a second subthreshold current flowing through the first transistor, reading a first source voltage corresponding to a first value of the first subthreshold current and. a second source voltage corresponding to a second value of the second subthreshold current equal to the first value and calculating the ratio of the difference between the first drain voltage and the second drain voltage to the difference between the first source voltage and the second source voltage thereby obtaining the coupling coefficient between the first gate electrode and the source region.
The coupling coefficient measuring method accordin
Arent Fox Kintner & Plotkin & Kahn, PLLC
Le Thong Q.
Sanyo Electric Co,. Ltd.
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