Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-09-28
2002-05-21
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185330
Reexamination Certificate
active
06392926
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit for protecting a flash memory, and particularly to a NMOS coupling circuit for preventing gate junction breakdown of flash memories.
2. Description of Related Art
In the modem industry, coupling circuits of flash memories could be classified into PMOS and NMOS types. The main disadvantage of a PMOS circuit is to have a weak noise immunity, which would cause an erroneous action. On the contrary, a NMOS circuit has stronger noise immunity. However, the breakdown voltage of gate junctions of a NMOS device is less than that of a PMOS circuit so that the gate junctions of a NMOS device cannot be applied by a large voltage.
FIG. 1
shows a NMOS coupling circuit of a prior art in flash memory. The front stage of the coupling circuit
10
is a decoding circuit (not shown), and the rear stage is a flash memory block (not shown) composed of a lot of flash memory unit cells. Two clock signals CLK and CLK_B are input to a third transistor
14
and a fourth transistor
16
through a first coupling capacitor
13
and a second coupling capacitor
15
, respectively. A signal ENB_B comes from the decoding circuit and is input to the gate of a fifth transistor
17
. When a unit cell corresponding to the coupling circuit is decoded by the front-stage of the decoding circuit, a corresponding signal ENB_B turns to logic one; otherwise, the signal ENB_B stays logic zero. A conducting stage
18
includes a first transistor
11
and a second transistor
12
whose drains are electrically connected to a high voltage HV outputted from a charge pump, and the gates of the first and second transistors
11
and
12
are electrically connected to the drain of the fifth transistor
17
. The source of the first transistor
11
outputs a high voltage VEP acting as a power source of the rear-stage flash memory block. When the coupling circuit
10
has not been decoded yet, the signal ENB_B is logic zero and the fifth transistor
17
is active, causing the gate voltages (X point) of the first transistor
11
and the second transistor
12
to be close to 0 Volt. Relative to the high voltage HV at the drain, the drain-gate junction of the first transistor
11
and the second transistor
12
will be loaded with a large voltage difference and thus effect the reliability of the flash memory. If the voltage difference is larger than the breakdown voltage of the flash memory, the first transistor
11
and the second transistor
12
would even be punched through and fail to work.
For eliminating the disadvantages of the prior art, the present invention proposes a novelty coupling circuit for flash memory to overcome the above drawbacks.
SUMMARY OF THE INVENTION
A main object of the present invention is to propose a coupling circuit for preventing gate junction breakdown in a flash memory.
To obtain the above purpose, the present invention adds at least one isolating stage between a conducting stage and a high voltage HV of the prior coupling circuit, and the addition generates a benefit that the voltage difference of the high voltage HV is burdened by both the conducting stage and the isolating stage of the coupling circuit. In other words, the voltage difference in the gate junction of the conducting stage will be reduced, and the probability of punching through a transistor will also be reduced. For reducing the effect of an instant voltage difference when the high voltage HV is enabled, the present invention electrically connects one end of a diode to the gate of the isolating stage, and electrically connects another end of the diode to a lower power source VDD. Therefore, the magnitude of the VDD will be reduced from the instant voltage difference to protect the isolating stage from damaging when the high voltage HV is enabled.
Besides, the present invention could insert a coupling capacitor between the high voltage HV and the gate of the isolating stage to reduce an instant impulse when the high voltage HV is enabled. The present invention could add a discharge path from the gate of the isolating stage to the ground. When the high voltage HV is disabled, the discharge path will be activated to release extra charges accumulated in the gate junction of the isolating stage.
REFERENCES:
patent: 4306185 (1981-12-01), Leuschner
patent: 5493244 (1996-02-01), Pathak et al.
patent: 5946175 (1999-08-01), Yu
patent: 6096610 (2000-08-01), Alavi et al.
patent: 6108181 (2000-08-01), Gerosa
patent: 6160739 (2000-12-01), Wong
Ladas & Parry
Tran Andrew Q.
Winbond Electronics Corporation
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