Coupling charge compensation device for VLSI circuits

Details Coupling charge compensation device for VLSI circuits Coupling charge compensation device for VLSI circuits

1997-07-11

1999-05-04

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Signal transmission integrity or spurious noise override

327387, H03K 1704

Patent

active

059007664

ABSTRACT:
A circuit for reducing capacitive coupling between a culprit and a victim signal line is provided which comprises two inverters, a n-channel FET connected as a capacitor, and a p-channel FET connected as a capacitor. The input of both inverters are connected to the culprit line. The first inverter is designed to respond to high-to-low transition on the culprit line more rapidly than a low-to-high transition. The output of the first inverter is connected to the drain and source of the n-channel FET. The gate of the n-channel FET is connected to the victim line. The second inverter is designed to respond to low-to-high transition on the culprit line more rapidly than a high-to-low transition. The output of the second inverter is connected to the drain and source of the p-channel FET. The gate of the p-channel FET is connected to the victim line.

REFERENCES:
patent: 5091661 (1992-02-01), Chiang
patent: 5774405 (1998-06-01), Tomishima
Patent Abstracts of Japan, vol. 014, No. 268 (E-0939), Jun. 11, 1990 and JP 02 084817 A (NEC Corp), Mar. 26, 1990, abstract; figure 2.

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