Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Including adhesive bonding step
Reexamination Certificate
2002-10-31
2003-12-30
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Including adhesive bonding step
C438S119000, C438S122000
Reexamination Certificate
active
06670223
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates, in general, to electronic packages, and particularly organic laminate chip carrier packages which mount encapsulated semiconductor chips, such as plastic ball grid array (PBGA) packages. These may provide for the mounting of so-called flip-chips, and wherein the chips are usually overlaid with a heat spreading cap designed to balance the coefficients of thermal expansion (CTE) and the stiffness of a substrate which is exposed on sides opposite of the chips. This is intended to compensate for mismatches in the coefficients of thermal expansion, resulting in contractions which cause the entire package arrangement to warp, leading to delamination between an encapsulant and cap and resulting in failure of connect joints and the ball grid arrays.
The concept of compensating for any mismatches in coefficients of thermal expansion (CTE) and resultant contractions which are encountered between the various components of a wire bond or flip chip package or module including encapsulated semiconductor chips mounted on substrates has been addressed in the technology. In this connection, heat sinks supported on the chips in the form of caps in order to reduce heat-induced bending or warpage tending to separate the components and leading to failures of the electrical connects and ball grid arrays adversely affecting the functioning and reliability of the packages has also been widely addressed in the technology and industry. The foregoing difficulties are encountered due to package warping as a result of thermal stresses generated, in that the normally utilized adhesives which cement the chip and cap to the substrate may possess coefficients of thermal expansion (CTE) which do not match and are substantially different from the coefficients of thermal expansion of the substrate. One of the possible failure mechanisms is delamination of the epoxy or adhesive interface between the chip and the cap as a result of thermally induced thermal stresses. Also, the tendency of the epoxy adhesive to absorb or desorb moisture may readily cause delamination by either increasing interfacial stresses at the cap and chip, or by degrading the strength of these interfaces.
2. Discussion of the Prior Art
At this time, various types of structures have been employed in the technology which concern themselves with the provision of means for dissipating heat which is generated during the operation of the module, and to minimize any potential module warpage or bending which can lead to operative failure and/or reduction in the service life thereof.
In particular, the semiconductor chips have been equipped with superimposed heat sinks in the form of so-called caps or covering structures which are adhesively fastened thereto; for example, such as through the interposition of an epoxy adhesive or the like, and wherein the caps extend generally above the areas defined by the surface extent of the chips. Such caps are normally constituted of a solid heat-conductive material, such as steel or copper. Other types of caps may incorporate multiple laminated layers of different materials or have fins formed thereon, providing enlarged surface areas for dispersing and dissipating heat, whereas other structures may have the caps extending beyond the confines of the chip and be suitably shaped to theoretically optimize the rate of heat dissipation from the module arrangements.
Among various publications which address themselves to the problems encountered caused by the formation of such interfacial stresses causing delamination of the module components, are Caletka et al. U.S. Pat. No. 6,104,093. This patent discloses a thermally enhanced and mechanically balanced flip chip package in which there is a balancing effected in the stiffness between and the coefficients of thermal expansion (CTE) of both a thermally conductive member and a laminate substrate.
Similarly, Johnson U.S. Pat. Nos. 5,883,430 and 5,726,079 also direct themselves to solving the problems of potential delamination between the module components of thermally-enhanced electronic flip-chip packages.
Tokuno et al U.S. Pat. No. 5,777,847 discloses a multichip module including a metallic cover plate fastened by means of a support pillar to a substrate, and wherein the plate is constituted of a heat conductive material, preferably such as copper or other suitable metal, such as aluminum or an aluminum alloy.
Marrs U.S. Pat. No. 5,485,037 discloses a heat sink in the form of a cap or cover structure arranged above a semiconductor chip which is mounted on a substrate, and which includes a plurality of holes adapted to be filled with a suitable filler material facilitating the dissipation of heat in a generally uniformly dispersed manner across the surface of the chip while maintaining the essential rigidity or stiffness of the heat sink or cap.
Baska et al U.S. Pat. No. 5,745,344 discloses a heat-dissipating apparatus including spaced fins for absorbing heat generated by an electronic device.
Liberty et al U.S. Pat. No. 5,213,868 is directed to a thermally conductive interface material of a polymeric binder and one or more thermal filters so as to form a heat sink for an electronic component.
Other types of structures which are adapted to be employed as heat sinks and which are arranged above encapsulated semiconductor chips and fastened thereto through the intermediary of epoxy adhesives, which may include heat conductive greases, including cap configurations incorporating pluralities of holes in varying specified sizes and arrays, and also scallops formed along the edges of the caps extending over the edge portions of the chips located therebeneath so as to allow for improved degrees of heat dissipation therefrom. Thus, for example, a thermally-enhanced heat-dissipating cap structure providing excellent mechanical interconnection of the components is disclosed in copending Caletka and Johnson patent application Ser. No. 09/430,075; filed Oct. 29, 1999, (Attorney Docket No.: END919980109US1) which is commonly assigned to the present assignee and the disclosure of which is incorporated herein by reference.
The foregoing types of cap or cover constructions are intended to form heat sinks are adept at dissipating heat from the semiconductor chips and ball grid arrays, but do not maintain package flatness. Other types of package constructions, in which the caps or cover structures forming the heat sink mounted above the chips reduce warpage and potential failure of the ball grid arrays and the entire package modules, have been found to delaminate. Further improvements in design and construction would still further enhance the adhesion of the caps while maintaining package flatness, thereby increasing the service life of the package module or electronic module arrangement.
SUMMARY OF THE INVENTION
In particular, pursuant to the invention, there is contemplated the provision of a novel heat-dissipating and structural balancing cap mounted above an encapsulated chip of an electronic package, wherein the cap preferably extends beyond the edges or confines of the chip, and may be essentially constituted of a unique mesh structure, rather than being formed from a solid material.
With the currently employed coupled cap design stresses between the cap and structural adhesive result in delamination after the ingress of moisture, or just due to solder reflow, or because of thermal cycling. Modeling has evidenced that it is the combination of the CTE and in-plane stiffness of the cap that balances the laminate while it is the bending stiffness of the cap and the expansion of the epoxy (with both due to effects of temperature and moisture) which control the interfacial stresses that produce delamination. For the present invention, for the cap the in-plane stiffness has been maximized and the bending stiffness minimized by preferably selecting a high-modulus material, such as steel, for the cap. Other materials, such as ceramics, also have a high modulus but may have a CTE that is too low to effective
Gaynes Michael Anthony
Johnson Eric Arthur
Nelms David
Nguyen Dao H.
Scully Scott Murphy & Presser
Steinberg William H.
LandOfFree
Coupled-cap flip chip BGA package with improved cap design... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Coupled-cap flip chip BGA package with improved cap design..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Coupled-cap flip chip BGA package with improved cap design... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3171733