Counteracting overtunneling in nonvolatile memory cells

Details Counteracting overtunneling in nonvolatile memory cells Counteracting overtunneling in nonvolatile memory cells

2007-03-29

2009-08-11

Nguyen, Dang T (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S104000, C365S149000

Reexamination Certificate

active

07573749

ABSTRACT:
Methods and apparatuses prevent overtunneling in nonvolatile floating gate memory (NVM) cells. An individual cell includes a circuit with a transistor that has a floating gate that stores charge, and a capacitor structure for extracting charge from the gate, such as by tunneling. A counteracting circuit prevents extracting charge from the floating gate beyond a threshold, therefore preventing overtunneling or correcting for it. In one embodiment, the counteracting circuit supplies electrons to the floating gate, to compensate for tunneling beyond a point. In another embodiment, the counteracting circuit includes a switch, and a sensor to trigger the switch when the appropriate threshold is reached. The switch may be arranged in any number of suitable ways, such as to prevent a high voltage from being applied to the capacitor structure, or to prevent a power supply from being applied to a terminal of the transistor or to a well of the transistor.

REFERENCES:
patent: 4935702 (1990-06-01), Mead et al.
patent: 4953928 (1990-09-01), Anderson et al.
patent: 5146106 (1992-09-01), Anderson et al.
patent: 5168464 (1992-12-01), Stanchak et al.
patent: 5301150 (1994-04-01), Sullivan et al.
patent: 5596524 (1997-01-01), Lin et al.
patent: 5616942 (1997-04-01), Song
patent: 5617358 (1997-04-01), Kodama
patent: 5623442 (1997-04-01), Gotou et al.
patent: 5627392 (1997-05-01), Diorio et al.
patent: 5650966 (1997-07-01), Cleveland et al.
patent: 5687118 (1997-11-01), Chang
patent: 5706227 (1998-01-01), Chang et al.
patent: 5736764 (1998-04-01), Chang
patent: 5754471 (1998-05-01), Peng et al.
patent: 5761121 (1998-06-01), Chang
patent: 5763912 (1998-06-01), Parat et al.
patent: 5777361 (1998-07-01), Parris et al.
patent: 5786617 (1998-07-01), Merrill et al.
patent: 5825063 (1998-10-01), Diorio et al.
patent: 5841165 (1998-11-01), Chang et al.
patent: 5844300 (1998-12-01), Alavi et al.
patent: 5892709 (1999-04-01), Parris et al.
patent: 5898613 (1999-04-01), Diorio et al.
patent: 5912842 (1999-06-01), Chang et al.
patent: 5969987 (1999-10-01), Blyth et al.
patent: 5990512 (1999-11-01), Diorio et al.
patent: 6028789 (2000-02-01), Mehta et al.
patent: 6049229 (2000-04-01), Manohar et al.
patent: 6055185 (2000-04-01), Kalnitsky et al.
patent: 6081451 (2000-06-01), Kalnitsky et al.
patent: 6137721 (2000-10-01), Kalnitsky et al.
patent: 6137722 (2000-10-01), Kalnitsky et al.
patent: 6137723 (2000-10-01), Bergemont et al.
patent: 6137724 (2000-10-01), Kalnitsky et al.
patent: 6166954 (2000-12-01), Chern
patent: 6208557 (2001-03-01), Bergemont et al.
patent: 6222771 (2001-04-01), Tang et al.
patent: 6252802 (2001-06-01), Kramer et al.
patent: 6294810 (2001-09-01), Li et al.
patent: 6320788 (2001-11-01), Sansbury et al.
patent: 6385000 (2002-05-01), Ottesen et al.
patent: 6385090 (2002-05-01), Kitazaki
patent: 6452835 (2002-09-01), Diorio et al.
patent: 6534816 (2003-03-01), Caywood
patent: 6678190 (2004-01-01), Yang et al.
patent: 6898123 (2005-05-01), Owen
patent: 6909389 (2005-06-01), Hyde et al.
patent: 6950342 (2005-09-01), Lindhorst et al.
patent: 7046549 (2006-05-01), Lee et al.
patent: 2003/0206437 (2003-11-01), Diorio et al.
patent: 2003/0222309 (2003-12-01), Roy et al.
patent: 2004/0004861 (2004-01-01), Srinivas et al.
patent: 2004/0037127 (2004-02-01), Lindhorst et al.
patent: 2004/0052113 (2004-03-01), Diorio et al.
patent: 2004/0206999 (2004-10-01), Hyde et al.
patent: 2005/0030827 (2005-02-01), Gilliland et al.
patent: 2006/0221715 (2006-10-01), Ma et al.
patent: 2007/0252701 (2007-11-01), Berry et al.
patent: 0778623 (2001-07-01), None
Chang, et al., “A CMOS-Compatible Single-Poly Cell for Use as Non- Volatile Memory,” International Semiconductor Device Date Research Symposium, Dec. 1-3, 1999, pp. 50-57.
Lanzoni et al., “A Novel Approach to Controlled Programming of Tunnel-Based Floating-Gate MOSFET's,” 1994, IEEE Journal of Solid-State Circuits, vol. 29, No. 2, pp. 147-150.
Diorio, “A p-Channel MOS Synapsse Transistor with Self-Convergent Memory Writes,” IEEE Transactions On Electron Devices, Vo. 47, No. 2, pp. 464-472, Feb. 2000.
Ohsaki et al., “A Single Poly EEPROM Cell Structure for Use in Standard CMOS Processes,” IEEE Journal of Solid-State Circuits, vol. 29, No. 3, Mar. 1994, pp. 311-316.
International Search Report for International Application No. PCT/US03/23724, dated mailed Jan. 20, 2004.
International Search Report for International Application No. PCT/US2005/013644, date mailed Aug. 3, 2005.

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