Electrical pulse counters – pulse dividers – or shift registers: c – Pulse counting or dividing chains
Reexamination Certificate
2000-08-14
2002-04-23
Lam, Tuan T. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Pulse counting or dividing chains
C327S141000, C710S033000, C710S061000
Reexamination Certificate
active
06377650
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the field of computer data bus systems, and more particularly to a counter register monitor and update circuit for a dual clock system.
BACKGROUND OF THE INVENTION
Computers, digital cameras, printers and scanners demand reliable, high speed communications. The trend in computerized systems is toward increasing communication speeds and decreasing bandwidth requirements. Imaging and video signals require precise synchronization of communications in order to prevent jittery graphics due to lost frames or other synchronization problems.
Computer systems may use bus transactions to communicate with an external system such as a printer. Most host systems include a counter register that generates a count. The host system may send counter register data to the external system. Within the computer system, communication takes place across the host data bus. The host data bus is a collection of wires through which data, a destination address, and other information is transmitted from one part of the computer to another. The host data bus is connected to a configuration block which contains several configuration and control registers, one of which includes a counter register. Although a counter register in the configuration block can be up to 32-bits wide, the host data bus is often 8 or 16-bits wide. Thus, multiple transfers are necessary in order to write and read the necessary information to the configuration block registers.
Although it is preferable to have the host data bus and the counter register to operate on the same clock source, thereby eliminating any clock synchronization issues, these two key components of a computer system often are attached to separate clock sources operating at different frequencies. Thus, before data and information from the host data bus can be transferred to the counter register, the two clock sources must be synchronized. When writing data to the counter register, there is a small amount of time when the data is not stable. A register that will contain a “1” after it has been stabilized may be read as a “0” during this unstable period. If the data is read during this time, the results are unpredictable. Reliable data transfer requires synchronization between the clocks so that the systems will not read unstable data or data communications may fail.
To eliminate the possibility of reading the counter register when it is in an unstable state, a process of handshaking must take place between the host data bus and the counter register. Handshaking is an exchange of a predetermined sequence of signals between two devices to establish synchronization between sending and receiving equipment for the purpose of exchanging data and status information.
Conventional handshaking solutions between the host data bus and the counter register provide low performance and low data throughput. A primary cause of the reduced performance and low throughput is the addition of bus cycles required to attain synchronization between the host data bus clock and the counter register clock. For example, bus cycles are lost waiting for the host bus request signal to become synchronized by the counter register clock. Similarly, the response sent by the counter register needs to be received under a synchronous environment with the host data bus clock before the transaction may be completed. The host bus wastes bandwidth by essentially “standing by” while waiting for handshaking to become synchronized, when it could perform other transactions. When accessing counter registers, there are at least two host bus clock cycles and three external system clock cycles which are wasted. With conventional handshaking each read transaction generally takes at least four host bus clock cycles and three external clock cycles and each write transaction generally takes at least four host clock cycles and three external clock cycles.
This clock synchronization process often results in a bottleneck of data and information waiting to be transferred to different parts of the computer. Additionally, since there is a constant change of the counter register during synchronization of the clocks, the value of the count retrieved from counter is not the accurate count of the register at the time the read request has been initiated. Some implementations of the clock synchronization process calculate the number of counter clock periods which have lapsed since the write/read request. However, this implementation requires more logic and, thus, is not cost effective solution.
Another computer system having clock synchronization, disclosed in our copending application, Ser. No. 60/116,623, filed Jan. 19, 1999, uses a post write buffer which is coupled to both the host data bus and the configuration block and functions to buffer the data in the host data bus until all registers in the configuration block are available to receive it. Since the data is buffered until all registers have been synchronized, the speed of data transfer is not optimum.
Thus, the current methods of connecting a host data bus and the counter register clocked by separate clock sources do not provide an efficient system, but one that often results in bottlenecks within the host data bus or substantial delay in the transfer of data.
SUMMARY OF THE INVENTION
From the foregoing, a need has arisen for an improved counter register and method of transferring data from a host data bus controlled by a first clock source to the counter register controlled by a second clock source which frees the host data bus to perform other functions while a clock synchronization process occurs to allow the data to be written to the counter register or read from the counter register. In accordance with the present invention to solve the long bus latency problem associated when a host data bus accesses a counter register, additional circuitry, such as, a post write/read buffer, control circuit, and sample and hold circuit, for a dual clock system is provided which substantially eliminates or reduces disadvantages or problems associated with conventional interconnections between a host data bus and counter register.
According to one embodiment of the present invention, there is provided a post write/read buffer which is coupled to both the host data bus and the counter register and functions to buffer the data of the host data bus until the counter register and the host data bus are ready to send or receive this data. At power up, automatic clear circuitry resets the post write/read buffer, the sample and hold register, the cycle timer and the control circuit.
The post read write buffer consists of a data buffer for each of the four bytes of data corresponding to the four bytes of the counter register or the host data bus. Control circuitry functions to synchronize the clocks while generating signals that determine which byte of data should be written or read and when internal data transfers should be made. The control circuit consists of an address decoder/write enable circuit and synchronization logic. The control circuit determines the states of the counter which is either of the three: idle, sample, or wait states.
The control circuit and post write/read buffer are set by the host data bus clock, while the sample and hold register and counter are set by the internal counter register clock. At the rising edge of the internal counter clock, the control circuit sends a flag to the sample and hold register to transfer the current count value from the cycle timer to the sample and hold register. The sample and hold register is coupled to the post write/read buffer such that the current counter value from the sample and hold register sits at the input of the post write/read buffer, however is not transferred to the buffers internal to the post write/read buffer. Upon the rising edge of the host data bus clock, the control circuit generates a second flag for the post write/read buffer to transfer the current count value at its input to its internal buffers.
During a write the data is stored in the post write/read b
Deng Brian T.
McKinney Michael D.
Brady W. James
Lam Tuan T.
Mosby April
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Counter register monitor and update circuit for dual-clock... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Counter register monitor and update circuit for dual-clock..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Counter register monitor and update circuit for dual-clock... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2933360