Counter register implementation for speculative execution of bra

Details Counter register implementation for speculative execution of bra Counter register implementation for speculative execution of bra

1993-01-08

1995-05-30

Coleman, Eric

Boots, shoes, and leggings

3642624, 3642631, 3642617, 364247, 364DIG1, 395375, G06F 922

Patent

active

054210208

ABSTRACT:
A data processing system for speculatively executing instructions. The data processing system includes a memory for storing instructions at addresses which can be generated by a branch unit in a processor. The processor also has a count register for storing an update value, a dispatch version value and a completion version value. A fetcher connected to the branch unit fetches instructions from memory based upon addresses calculated by the branch unit. The branch unit handles processing of conditional branch instructions. To do so, means for initializing the update value and the dispatch version value for branch control are provided. Further included are means responsive to completion of initialization for copying the update value as the completion version value. The system further includes means responsive to dispatch of a conditional branch instruction for examining the dispatch version value to determine if a branch should be taken and then decrementing the dispatch version value. Means responsive to completion of the branch provide for decrementing contents of a completion version register. Finally, means responsive to occurrence of an interrupt prior to completion of the branch provide for replacing the dispatch version value with the completion version value to restore the system to a state prior to the speculative execution of instructions.

REFERENCES:
patent: 4760519 (1988-07-01), Papworth et al.
patent: 4920477 (1990-04-01), Colwell et al.
patent: 4942520 (1990-07-01), Langendorf
patent: 5101484 (1992-03-01), Kohn
patent: 5136696 (1992-08-01), Beckwith et al.
patent: 5142634 (1992-08-01), Fite et al.
"Implementing Precise Interrupts in Pipelined Processors", James E. Smith, et al., Transactions on Computers, May 1988, No. 5.
"Looping in MSIS", IBM Technical Disclosure Bulliten, vol. 36, No. 1, Jan. 1993, pp. 262-264.
"Parallelization of Loops With Exits on Pipelined Architectures", P. Tirumalai, et al. Supercomputing '90, Nov. 12, 1990, pp. 200-212.
Harold S. Stone, High-Performance Computer Architecture, Chapter 3, New York, U.S., 1987, pp. 150-155 and 168-171.

Affiliated with

Also associated with

Rating

Counter register implementation for speculative execution of bra does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Counter register implementation for speculative execution of bra, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Counter register implementation for speculative execution of bra will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-370023