Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Pulse multiplication or division
Reexamination Certificate
2008-06-27
2009-10-27
Lam, Tuan (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Pulse multiplication or division
C377S048000, C377S118000
Reexamination Certificate
active
07609800
ABSTRACT:
The present invention relates to a unit counter block. According to an aspect of the present invention, the unit counter block includes a D-flipflop, a second MUX, and a first MUX. The-flipflop outputs first and second output signals in synchronism with a clock signal. The second MUX selects any one of external data and the second output signal of the D-flipflop in response to a data load signal and outputs a selected signal. The first MUX transfers any one of the first output signal of the D-flipflop and the output signal of the second MUX as an input signal of the D-flipflop in response to a counter enable signal or the data load signal.
REFERENCES:
patent: RE39578 (2007-04-01), Lu
patent: 2002/0194558 (2002-12-01), Wang et al.
patent: 2003/0154434 (2003-08-01), Hou
patent: 2006/0044990 (2006-03-01), Kawabe et al.
patent: 2007/0075732 (2007-04-01), Fruhauf et al.
patent: 2007/0198101 (2007-08-01), Leung et al.
patent: 2008/0303544 (2008-12-01), Kawamura
patent: 2008/0316850 (2008-12-01), Penzes
Jeong Byoung Kwan
Lim Sang Oh
Yoon Mi Sun
Hynix / Semiconductor Inc.
Lam Tuan
Townsend and Townsend / and Crew LLP
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