Counter logic for multiple memory configuration

Details Counter logic for multiple memory configuration Counter logic for multiple memory configuration

2001-06-27

2002-07-16

Wambach, Margaret R. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Applications

Including memory

C377S002000, C377S016000, C377S051000

Reexamination Certificate

active

06421408

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of electronic memory design. More particularly, the present invention relates to a system and method for masking counter output bits to prevent them from incrementing.
BACKGROUND OF THE INVENTION
Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Numerous electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems have facilitated increased productivity and reduced costs in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. Electronic systems designed to provide these benefits often include counters that increment a value. The incremented values are utilized to support a variety of functions with differing incrementing requirements. Counters capable of providing flexible incrementation configurations to meet the variety of incrementation requirements offer significant advantages. One traditional method of attempting to achieve some flexibility in counting routines is to mask certain output bits of a counter. However, traditional attempts at masking counter output bits typically have relatively limited flexibility and require significant resources to implement.
Most electronic counters are digital and operate on signals representing logical ones and zeroes values. The logical values of a counter output word are typically utilized to form a binary number.
FIG. 1A
is a block diagram of a typical prior art 4 bit counter system
100
. A 4 bit counter system provides a counter output word comprising 4 bits that vary in significance from a least significant bit to a most significant bit. Prior art counter system
100
includes incrementor cells
111
through
114
which produce physical counter output bits
121
through
124
respectively. Counter output bit
121
is the most significant bit and counter output bit
124
is the least significant bit. Counter system
100
increments by 1 from a value of 0000 to 1111. Each incrementor cell performs the incrementation of a corresponding counter output bit depending upon a carry in value from the preceding incrementor cell and the value of the counter output bit during a previous cycle. Each incrementor cell also provide a carry output value which serves as the carry in value for the next incrementor cell.
One type of specialized counter is a burst counter. A burst counter performs an incrementation function by “adding” one to a previous value. Traditional burst counters are often limited in the counting routines they provide since they typically increment by a value of one. Modifying a burst counter to provide additional functionality such as incrementing by a different number typically requires significant additional circuit resources. Burst counters are usually implemented on a silicon semiconductor chip with limited resources. Even when precious chip resources are committed to masking a counter output bit, the masking functionality of a traditional burst counter is very limited.
One approach to achieving additional functionality is to mask counter output bits but this is traditionally limited to masking a most significant bit or a least significant bit. In one traditional counter system with additional masking circuits a most significant bit is masked by preventing a new value from loading in the incrementor and presenting an old value as the counter output bit. One traditional counter system has an extended carry change with a shifter before the increment logic and another after the increment logic which permits incrementation by two instead of incrementing by one. The shifters enabled the traditional counter to mask a least significant bit by shifting down by one bit, incrementing and then shifting up by one bit.
The shifters and counter interrupt logic usually consume significant precious integrated circuit resources to implement. The shifters in a traditional burst counter circuit are usually implemented with a plurality of multiplexers that include numerous logic gate circuits and have separate logic to generate the counter interrupt. These extra traditional circuit resources are typically limited to masking least significant bits or most significant bits. In theory some traditional burst counter circuits providing maskable counter bit functionality could be extended to shift by a plurality of consecutive least or most significant bits which would allow incrementation by powers of 2 (e.g., 4 or 8). However, this theoretical expansion would require an even greater number of additional circuits and consume even greater amounts of precious chip resources. Despite resource consumption, the ability to have flexible masking capabilities is often very important in a variety of implementations, such as utilizing burst counter in memories.
Electronic systems often include memory components for storing information. Information is typically stored in certain areas or locations of a memory referred to as a memory cell. Each memory cell is usually identified by a unique sequential address. Addresses are usually established by incrementing an address counter and it is often advantageous to mask certain bits in the counter, for example to change the logical length of an address counter. In some applications, multiple memory cells are downloaded at a. the same time and the ability to increment the counter by a higher power of 2 permits simplified address decoding. Each memory typically has a maximum number of bits it is capable of storing and the size of each memory cell (e.g., the depth) determines the configuration of the memory within the maximum bit limit. For example, a maximum bit storage value divided by the size or width of the cell determines the number of cells included in a memory and since each cell is identified by a unique address it also provides the number of unique address required by the memory system.
FIG. 1B
is a tabular listing of the physical and corresponding logical address mapping for different exemplary memory configurations.
What is required is an efficient system and method for flexible masking of output bits from a counter.
SUMMARY
The present invention is an efficient system and method for flexible masking of output bits from a counter. The maskable counter system and method of the present invention modify the chain carry fed into a counter so that any bit (or bits) of the counter may be masked. In one embodiment of the present invention, the masked bits are user programmable. A masked bit of a maskable counter system and method of the present invention is utilized in one implementation to facilitate user programmable control of multiple configurations in a memory. In one embodiment of the present invention, a maskable counter system comprises a mask register (e.g., a D flip flop), a counter (e.g., a D flip flop), and a masking coordination circuit. The masking coordination circuit permits a carry in signal, a carry out signal, a local carry lookahead signal and a counter output bit signal to operate in a normal incrementation manner if a mask bit is not asserted and prevents the counter output bit signal from changing if the mask bit is asserted. The mask register stores the mask bit and the counter provides a counter output bit signal. In one embodiment, the present invention also has an option input that facilitates changing one die into different configurations and masking any counter output bit in a counter output word (including most significant bits, least significant bits, and bits other than the most significant or least significant).


REFERENCES:
patent: 6253307 (2001-06-01), Boutaud et al.

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