Electrical pulse counters – pulse dividers – or shift registers: c – Particular transfer means – Including logic circuit
Patent
1989-03-31
1990-11-27
Heyman, John S.
Electrical pulse counters, pulse dividers, or shift registers: c
Particular transfer means
Including logic circuit
307279, 307289, 307471, 377104, 377117, 377111, H03K 2102, H03K 2344
Patent
active
049742418
ABSTRACT:
The synchronization circuit of the preferred embodiment is a T flip flop which has a first output which changes state on the leading edge of the clock signal, and a second output which changes state on the trailing edge of the clock signal. The T flip flop has an exclusive OR gate input in which the T input is combined with the first output. The output of the exclusive OR is coupled to an internal node when the clock signal is at a first logic state, and isolated from the internal node when the clock signal is at a second logic state. The internal node is coupled to the first output when the clock signal is at the second logic sate and isolated from the internal node when the clock signal is at the first logic state. The first output signal is coupled to the second output signal when the clock signal is at the first logic state, and isolated from the second output terminal when the clock signal is at the second logic state.
REFERENCES:
patent: 3930169 (1975-12-01), Kuhn
patent: 4495628 (1985-01-01), Zasio
patent: 4703200 (1987-10-01), Zangara
patent: 4843254 (1989-06-01), Motege et al.
Lysinger Mark A.
McClure David C.
Heyman John S.
Hill Kenneth C.
Lott Robert D.
Robinson Richard K.
SGS-Thomson Microelectronics Inc.
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