Counter-doped transistor

Fishing – trapping – and vermin destroying

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437 34, 437 56, 437 57, 437 41, 437 27, 437 28, 437 29, 357 233, H01L 21265, H01L 2170

Patent

active

049083279

ABSTRACT:
P channel and N channel CMOS FETs (22, 24) and a process for their simultaneous fabrication with a minimal number of masking steps are disclosed. After formation of gates (30, 32) for both P channel FETs (24) and N channel FETs (22), a first N type dopant implanting step forms lightly doped drain extensions in both the P channel FETs (24) and the N channel FETs (22). A mask then protects the N channel FET area (22) while a P type dopant is implanted in source and drain regions (36) of the P channel FET (24) at a greater concentration than the prior implanted N type dopant. Another N type dopant implant occurs to both the P channel FET (24) and N channel FET (22). The N type dopant dosage used in this second N type dopant implantation step is greater than the dosage used in the first N type dopant implantation step. Another mask is used to protect the N channel FET (22) while a second P type dopant is implanted into source and drain regions of the P channel FET (24) at a greater concentration than is used in any of the previous implantation steps. Due to the high diffusion rate of the P type dopant, an annealing step drives the P type dopant so that the P channel FET (24) source and drain regions (36) reach the active transistor region underneath the gate.

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