Electrical pulse counters – pulse dividers – or shift registers: c – Starting – stopping – presetting or resetting the counter
Reexamination Certificate
1999-11-09
2001-04-24
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Starting, stopping, presetting or resetting the counter
C377S027000, C377S044000
Reexamination Certificate
active
06222900
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a counter device comprising a master counter and a plurality of functional blocks each including a local counter.
2. Description of the Prior Art
An increase in the packing density of LSIs increases power consumption in wiring, thus exerting a large influence upon the power consumption in the whole of one chip. In one-chip devices, such as system LSIs, including a plurality of functional blocks, the length of wiring for connecting them with each other increases with increases in the number of the plurality of functional blocks. It is thus important to reduce power consumption in wiring through which a signal to be referred in common by the plurality of functional blocks is passed.
System LSIs have a plurality of blocks formed in units of functionality and a common time to cause the plurality of functional blocks to operation in cooperation with one another. For example, in a system which conforms to the Read-only DVD Standard, a plurality of decoders (for Video Sub-picture, PCI, Audio) can refer to System Time Clock or STC. The STC is a timer whose value periodically varies.
When each of a plurality of blocks refers to STC within one chip device in which a master counter is provided for enabling each of the plurality of blocks to refer to the STC, as shown in
FIG. 5
, that is, each of the plurality of blocks refers to the contents of the master counter, a bus connecting the master counter with the plurality of blocks frequently changes in voltage, thus increasing the power consumption in the bus.
Referring now to
FIG. 6
, there is illustrated a block diagram of another prior art counter device in which a plurality of functional blocks include respective counters that can be brought into synchronization with each other by a common control signal (or reset signal). The prior art counter device can reduce the power consumption because it does not include a bus for connecting a master counter with the plurality of functional blocks. However, since each of the plurality of functional blocks needs its own counter, the amount of hardware is increased.
A problem with a prior art counter device as shown in
FIG. 5
is that each of a plurality of functional blocks needs to refer to a master counter, such as a timer counter, whose count value periodically, frequently changes, and therefore a bus for connecting the master counter with the plurality of blocks frequently changes in voltage or value, thus increasing the power consumption. Further, a problem with another prior art counter device, as shown in
FIG. 6
, in which a plurality of functional blocks include respective counters, is that although the power consumption can be reduced because no bus is needed for connecting a master counter with the plurality of functional blocks, the amount of hardware is increased.
SUMMARY OF THE INVENTION
The present invention is made to overcome the above problems. It is therefore an object of the present invention to provide a counter device capable of reducing the number of times that a bus for connecting a master counter with a plurality of functional blocks changes in voltage, thus decreasing the power consumption in the bus.
In accordance with one aspect of the present invention, there is provided a counter device comprising: a master counter for counting an input signal applied thereto; a plurality of local counters disposed in a plurality of functional blocks, respectively, each for counting the input signal applied thereto, and for holding a count value corresponding to a plurality of bits of a count value of the master counter; and a bus used for each of the plurality of functional blocks to refer to remaining bits of the count value of the master counter. The counter device can thus reduce the number of times that the bus changes in voltage or value, thus reducing the power consumption in the bus. In addition, since each of the plurality of functional blocks only has the local counter with a plurality of bits only required for holding the binary value of the specified bits of the count value of the master counter, thus reducing the amount of hardware.
Preferably, the plurality of bits of the count value of the master counter are a plurality of lower-order bits of the count value of the master counter.
The input signal can be a clock. As an alternative, the input signal is a counter control signal supplied from outside the counter device or generated by another functional block built in one chip including the counter device, the counter control signal being generated based on a sequence of events.
In accordance with another aspect of the present invention, there is provided a counter device comprising: a master counter for counting an input signal applied thereto; a plurality of local counters disposed in a plurality of functional blocks, respectively, each for counting the input signal applied thereto, and for holding a count value corresponding to a plurality of bits of a count value of the master counter; a bus used for each of the plurality of functional blocks to refer to remaining bits of the count value of the master counter; and a counter setting unit, responsive to a control signal, for setting the master counter at a predetermined count value and for setting each of the plurality of local counters at a value of the plurality of bits of the predetermined count value. The counter device can thus set an arbitrary count value to the master counter and the plurality of local counters.
Preferably, the plurality of bits of the count value of the master counter are a plurality of lower-order bits of the count value of the master counter.
In accordance with a preferred embodiment of the present invention, the counter setting unit includes a bus used for supplying the value of the plurality of bits of the predetermined count value to each of the plurality of local counters so as to allow each of the plurality of local counters to set itself at the value of the plurality of bits of the predetermined count value in response to the control signal.
In accordance with another preferred embodiment of the present invention, the counter setting unit causes each of the plurality of local counters to reset itself in response to the control signal, and, after that, causes the master counter to start counting from the predetermined count value when each of the plurality of local counters reaches the value of the plurality of bits of the predetermined count value. Preferably, the counter setting unit includes a counter that resets itself in response to the control signal, the counter holding a count value equal to the count value of each of the plurality of local counters, and a unit for allowing the master counter to start counting from the predetermined count value when the counter of the counter setting unit reaches the value of the plurality of bits of the predetermined count value. The counter device can thus set an arbitrary count value to the plurality of local counters without having to provide another bus intended for setting the count value of each of the plurality of local counters.
The input signal can be a clock. As an alternative, the input signal is a counter control signal supplied from outside the counter device or generated by another functional block built in one chip including the counter device, the counter control signal being generated based on a sequence of events.
Further objects and advantages of the present invention will be apparent from the following description of the preferred embodiments of the invention as illustrated in the accompanying drawings.
REFERENCES:
patent: 4631484 (1986-12-01), Malka et al.
patent: 7-134187 (1995-05-01), None
Burns Doane , Swecker, Mathis LLP
Mitsubishi Denki & Kabushiki Kaisha
Wambach Margaret R.
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