Electrical computers and digital processing systems: processing – Processing architecture – Distributed processing system
Reexamination Certificate
2005-06-22
2009-02-10
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Distributed processing system
C712S214000
Reexamination Certificate
active
07490219
ABSTRACT:
In the present invention, in order that a busy judgment of a register can be made without fail and without increasing the number of hardware resources for storing a request into the register provided at the final stage of a pipeline register in a stage in which the request is retained halfway in the pipeline register in a pipeline processor, a first counter for counting the number of valid requests in the registers between a judgment section interposed in the pipeline register and for judging whether the request is a valid request and a request queue and a busy judgment section for judging whether the request queue is in a busy state based on the number of valid requests counted by the first counter are provided and a judgment is made by the judgment section based on the result of the busy state judgment by the busy judgment section.
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European Search Report dated Dec. 21, 2007 for corresponding European Patent Application No. 05013582.1-1243.
Hataida Makoto
Hosokawa Yuka
Matsui Takao
Okada Seishi
Ueki Toshikazu
Chan Eddie P
Faherty Corey S
Fujitsu Limited
Staas & Halsey , LLP
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