Counter-controlled delay line

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform

Reexamination Certificate

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Details

C327S265000

Reexamination Certificate

active

07071751

ABSTRACT:
A counter-controlled delay line for delaying signals having a wide range of possible frequencies is described. The counter-controlled delay line receives an input clock and produces a delayed output clock based on a delay select control signal. The delay select control signal includes three granularities of delay: a coarse grain, medium grain, and fine grain. The coarse grain delay is provided by a counter. The medium grain delay is provided by a sequential starter circuit coupled to an oscillator. The fine grain delay is provided by a trim unit.

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U.S. Appl. No. 10/954,889, filed Sep. 29, 2004, Kaviani et al.
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Xilinx, Inc.; “Virtex-II Platform FPGA Handbook”; published Dec. 2000; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 161-183.
U.S. Appl. No. 11/015,322, filed Dec. 17, 2004, Kaviani.

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