Static information storage and retrieval – Addressing – Counting
Reexamination Certificate
2007-03-23
2008-11-04
Nguyen, Dang T (Department: 2824)
Static information storage and retrieval
Addressing
Counting
C365S233100, C365S191000
Reexamination Certificate
active
07447111
ABSTRACT:
A counter control signal generating circuit is disclosed. The circuit includes a first counter configured to receive a latched external address, and count the latched external address for a first latency, thereby generating a first counted address, a second counter for counting the first counted address for a second latency, thereby generating a second counted address, a counter control signal generator configured to receive a write recognition signal, which is enabled in response to a write command, and generate a counter control signal for controlling enabling of the second counter, in response to the write recognition signal, a first detecting signal generator configured to receive the write recognition signal, generate a first command signal obtained after counting of the write recognition signal for the first latency, and generate a first detecting signal, which is enabled in response to the write recognition signal, and a second detecting signal generator configured to receive the first command signal, generate a second command signal obtained after counting of the first command signal for the second latency, and generate a second detecting signal, which is enabled in response to the first command signal.
REFERENCES:
patent: 6229759 (2001-05-01), Morgan
patent: 6564287 (2003-05-01), Lee
patent: 7164287 (2007-01-01), Ueno
patent: 7171323 (2007-01-01), Shipton et al.
patent: 2006/0203605 (2006-09-01), Lee
patent: 10-2007-0095563 (2007-10-01), None
Cooper & Dunham LLP
Hynix / Semiconductor Inc.
Nguyen Dang T
White John P.
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