Counter control circuit in a burst memory

Details Counter control circuit in a burst memory Counter control circuit in a burst memory

1995-11-07

1998-02-24

Moore, David K.

Static information storage and retrieval

Magnetic bubbles

Guide structure

39542108, 395401, 365233, 36518905, 36523001, G06F 926, G06F 1200

Patent

active

057218595

ABSTRACT:
An integrated memory circuit is described which can be operated in a burst access mode. The memory circuit includes an address counter which changes column addresses in one of a number of predetermined patterns. The column address is changes in response to a rising edge of a column address signal (CAS*). The memory also includes a buffer circuit which latches the output of the address counter in response to the falling edge of the column address signal. Memory cells are accessed in a burst manner on the falling edge of the column address signal using the address latched in the buffer.

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