Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2000-10-26
2004-01-06
Malzahn, David H. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C377S037000
Reexamination Certificate
active
06675188
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a counter readout control apparatus and control method therefor, which is suitable for readout of a counter value having a bit width that is larger than the bit width that can be read by a CPU.
2. Related Art
In the prior art, when reading a counter value having a bit width that is larger than a data bus, it was necessary to divide the read cycle into a number of parts. For this reason, if there was a carry to an upper-order counter from the lowermost-order counter during the reading of all the counters, there was no assurance of the read value. Therefore, this problem was solved using software. For example, after reading all of the counters, the lowermost-order counter value was read, and a software check was made of whether the counter value of the lowermost-order counter is within a reasonable range, so as to make a judgment as to whether or not the read data is valid. More specifically, in the case of a lowermost-order counter having eight bits, if the first read value is between EFH and FFH, and if the second read value is between 00H and 0FH, the judgment is made that a carry has occurred to an upper-order counter from the lowermost-order counter, the overall counter value being taken as invalid. In other cases, however, the software takes the counter value as being valid.
FIG. 6
is a flowchart showing the read operation of a counter value in the prior art. In
FIG. 6
, the first read value is cread0_old, and the second read value is cread0_new, so that in step S
66
, the second read value cread0_new is compared with the first read value cread0_old. When performing this processing using software, it is possible that exceptional processing or the like occurs during reading of the entire counter, so that the desired software processing such as re-reading and the like is not performed for a long period of time. That is, software processing can become complex and, because of external influences, there are cases in which the counter value is not assured.
Accordingly, it is an object of the present invention to improve on the above-noted drawbacks of the prior art, by particularly providing a novel counter readout control apparatus and control method therefor that enables accurate reading of a counter value.
SUMMARY OF THE INVENTION
To achieve the above-noted object, the present invention has the following basic technical constitution.
Specifically, a first aspect of the present invention is a counter readout control apparatus comprising a plurality of counters, in which an upper-order counter performs a counting operation upon receiving a carry from a lower-order counter, the apparatus further comprising, a first means for resetting each flag storing memory in which a carry of each counter, with an exception of an uppermost-order counter, is stored (Step S
21
), a second means for sequentially reading out the plurality of counters from an upper-order counter to a lower-order counter (Step S
22
to S
25
), a third means for, after reading each counter value by means of the second means, testing as to whether the carry is set or not in the flag storing memory (Step S
26
to S
29
), and a fourth means for, in the case in which the carry is set in the flag storing memory, resetting the flag storing memory having the carry (Step S
27
A, S
28
A, S
29
A) and performing a re-read operation only of counters having an order higher than an order of a counter which has been changed due to a reception of the carry (Step S
22
to S
25
).
A second aspect of the present invention is a counter readout control method for a counter comprising a plurality of counters, in which an upper-order counter performs a counting operation upon receiving a carry from a lower-order counter, the method comprising, a first step of resetting each flag storing memory in which a carry of each counter, with an exception of an uppermost-order counter, is stored, a second step of sequentially reading out the plurality of counters from an upper-order counter to a lower-order counter, a third step of, after reading each counter value by means of the second means, testing as to whether the carry is set or not in the flag storing memory, and a fourth step of, in the case in which the carry is set in the flag storing memory, resetting the flag storing memory having the carry and performing a re-read operation only of counters having an order higher than an order of a counter which has been changed due to a reception of the carry.
REFERENCES:
patent: 4341950 (1982-07-01), Kyles et al.
patent: 4477918 (1984-10-01), Nossen et al.
patent: 4589019 (1986-05-01), Dischert et al.
patent: 57-107641 (1982-07-01), None
patent: 4-369726 (1992-12-01), None
patent: 05-191406 (1993-07-01), None
patent: 6-301440 (2000-10-01), None
patent: 1998-059774 (1998-10-01), None
patent: 10-0214399 (1999-08-01), None
Minami Masahiro
Ootsuka Shigekazu
Katten Muchin Zavis & Rosenman
Malzahn David H.
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