Counter circuit with two tri-state latches

Electrical pulse counters – pulse dividers – or shift registers: c – Particular transfer means – Including logic circuit

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Details

377121, 365236, H03K 2344

Patent

active

051310180

ABSTRACT:
A counter circuit is disclosed. The circuit has a first tri-state inverter for receiving data bits and their components. It includes a first tri-state latch for receiving the data bits and their complements, connected to the output of the first tri-state inverter. It has a second tri-state inverter for receiving the data bits and their complements that is connected to the output of the first tri-state latch. It includes a second tri-state latch for receiving the data bits and their complements. The second tri-state latch is connected to the output of the second tri-state inverter. Its output is the output of the circuit, and, its output is fedback to the first tri-state inverter. Such a circuit is useful in setting an internal address of a dynamic memory device during a CBR cycle.

REFERENCES:
patent: 4002926 (1977-01-01), Moyer
patent: 4068137 (1978-01-01), Vittoz
patent: 4114049 (1978-09-01), Suzuki
patent: 4568842 (1986-02-01), Koike

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