Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2009-05-18
2011-10-18
Le, Vu (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S236000
Reexamination Certificate
active
08040752
ABSTRACT:
To provide a counter circuit capable of accurately counting a high-frequency signal in which hazard or the like is easily generated. There are provided: a frequency dividing circuit that generates first and second frequency dividing clocks, which differ in phase to each other, based on a clock signal; a first counter that counts the first frequency dividing clock; a second counter that synchronizes with the second frequency dividing clock to fetch a count value of the first counter; and a selection circuit that exclusively selects count values of the first and second counters. According to the present invention, a relation of the count values between the first and second counters is kept always constant, and thus, even when hazard occurs, the count values are only made to jump and the count values do not fluctuate.
REFERENCES:
patent: 6388945 (2002-05-01), Aikawa
patent: 7345950 (2008-03-01), Fujisawa et al.
patent: 2008/0043566 (2008-02-01), Fujisawa
patent: 2008/0192563 (2008-08-01), Cho
patent: 2009/0323441 (2009-12-01), Johnson et al.
patent: 2007-115351 (2007-05-01), None
patent: 2008-047267 (2008-02-01), None
Elpida Memory Inc.
Le Vu
Sughrue & Mion, PLLC
LandOfFree
Counter circuit, latency counter, semiconductor memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Counter circuit, latency counter, semiconductor memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Counter circuit, latency counter, semiconductor memory... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4264995