Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Identifying or correcting improper counter operation
Reexamination Certificate
2001-08-15
2003-12-09
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Identifying or correcting improper counter operation
C377S030000, C377S046000, C377S116000
Reexamination Certificate
active
06661864
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a counter circuit with what is called a booby trap.
2. Description of the Background Art
One of circuits often used in a semiconductor integrated circuit is a Johnson counter. The Johnson counter has a configuration in which a plurality of flip flop circuits (hereinbelow, FF circuits) are connected in series and an output of the FF circuit at the final stage is input to the FF circuit at the first stage. Due to an influence of radiation from the space or the like, however, there is a case such that a value to be held by an arbitrary FF circuit is erroneously inverted. At this time, the counter outputs a value which is not inherently outputted, and an erroneous operation occurs. The Johnson counter having the function of recovering to a normal state by continuously operating even when the erroneous operation occurs is known. The function is generally called a booby trap.
FIG. 16
shows a conventional Johnson counter with the booby trap. This is the same as that disclosed in
FIG. 5
of publication of Japanese Patent Laying-Open No. 8-162946, and the booby trap is realized by one AND gate
2
and (n−2) OR gates
3
to n.
In the Johnson counter, a common clock signal is input to (n) FF circuits. Each of the FF circuits captures a logical value supplied at the timing of the rising edge of a waveform of a clock signal and holds and continuously outputs the logical value until the next rising edge of the clock signal. On the other hand, the logical value to be held next has to be determined and supplied to each of the FF circuits by the next rising edge of the clock signal.
The frequency of the clock signal is dramatically increasing as the processing speed of a circuit is becoming higher in recent years. In consideration of the circumstances, the logical value to be held next is requested to be supplied to the FF circuit as quickly as possible. In the Johnson counter shown in
FIG. 16
, however, particularly the value to be supplied to each of FF circuits #3 to #n is obtained by calculating the AND logic of outputs of the FF circuits #1 and #n by the AND logic gate
2
and subsequently computing the OR logic between the AND logic and an output of the FF circuit at the immediately preceding stage by each of the OR logic gates
3
to n. Signal propagation by the AND logic gate
2
and the OR logic gates
3
to n causes a delay in determination of a value to be input to each of the FF circuits. In other words, the AND gate
2
and the OR gates
3
to n provided for realizing a booby trap make designing of a counter circuit requiring high-speed operation difficult.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a counter circuit capable of operating at high speed.
The invention is, in short, directed to a counter circuit for counting clock signals, which has a plurality of counter stages cascaded for receiving common clock signals.
Each of the plurality of counter stages includes a flip flop circuit for capturing an input signal synchronously with the clock signal, and outputting an output signal according to the captured input signal.
At least one of the plurality of counter stages is a first arithmetic counter stage. The first arithmetic counter stage further includes a first two-input logic gate for receiving, as a first internal input signal, an output of the flip flop circuit included by the first arithmetic counter stage, receiving, as a second internal input signal, an output of the flip flop circuit included by a predetermined counter stage different from the first arithmetic counter stage in the plurality of counter stages, and outputting a result of logical operation of the first and second internal input signals to a counter stage at the post-stage of the first arithmetic counter stage.
Thus, a main advantage of the invention is that by employing a logic gate of two inputs, delay in signal input to a flip flop circuit can be reduced, and high speed operation can be realized.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5077764 (1991-12-01), Yamashita
patent: 5754615 (1998-05-01), Colavin
patent: 8-162946 (1996-06-01), None
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Wambach Margaret R.
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