Counter circuit

Details Counter circuit Counter circuit

1998-09-02

2000-08-08

Wambach, Margaret R.

Electrical pulse counters, pulse dividers, or shift registers: c

Particular output circuits for counter

377 28, 377116, H03K 2108

Patent

active

061012335

ABSTRACT:
Counter circuits causing no noise at the time of operation are provided. Three stage of D-type flip-flops (FF1 to FF3) are connected in series. A delay element (11) delays a signal (S2) that is Q output of the flip-flop (FF1) by a delay time (d2) to output a delay signal (S2D), and a delay element (12) delays a signal (S3) that is Q output of the flip-flop (FF2) by a delay time (d3) to output a delay signal (S3D). Here, the relationship among the delay time (d2, d3) and a clock cycle (Tc) is set so as to satisfy the condition of {Tc>d2>d3}. NOR gate for three inputs (G1) receives delay signals (S2D, S3D) and a signal (S4) i.e., Q output of the flip-flop (FF3), and performs NOR operation on these signals (S2D, S3D and S4), thereby outputting a signal (S1) to D input of the flip-flop (FF1).

REFERENCES:
patent: 4394769 (1983-07-01), Lull
patent: 4493095 (1985-01-01), Yazawa
patent: 4516251 (1985-05-01), Gallup
Noboru Ishihara, et al., "3.5Gb/s.times.4-Ch Si Bipolar LSIs for Optical Interconnections", 1995 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 34-35.
Phuc C. Pham, et al., "A 2.5Gb/s 32:1/1:32 Sonet Mux/Demux Chip Set", 1996 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 120-121.

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