Counter cell including a latch circuit, control circuit and a pu

Details Counter cell including a latch circuit, control circuit and a pu Counter cell including a latch circuit, control circuit and a pu

1991-04-01

1992-12-29

Miller, Stanley D.

Electrical pulse counters, pulse dividers, or shift registers: c

Phased clocking

Field-effect transistor

377104, 377111, 377114, 377117, 377121, H03K 238

Patent

active

051757532

ABSTRACT:
A counter cell includes a latch circuit, control circuit, and a pull-up circuit. The laatch circuit is formed of a first clocked half-latch (32), a second clocked half-latch (34) and an inverter (INV1) for storing a binary output signal. The first clocked half-latch (32) is responsive to a first clockk phase signal for transferring the binary output signal from its input to its output. The second clocked half-latch (34) is responsive to a second clock phase signal for transferring binary output signal from its input to its output. The control circuit is responsive to an input complement signal for selectively passing the first clock phase signal to the first clocked half-latch so as to permit toggling the state of the binary output signal. The pull-up circuit is responsive to the binary output signal and the input complement signal for generating an output complement signal. The logic value of the output complement signal is equal to the logic value of the input complement signal only when a binary output signal is at a high logic level. The logic value of the output complement signal is maintained at a high logic level when the binary output signal is at a low logic level. Any number of these counter cells can be arranged to form an N-bit counter circuit.

REFERENCES:
patent: 3657557 (1972-04-01), Smith et al.
patent: 4025800 (1977-05-01), Wanlass
patent: 4114052 (1978-09-01), Manabe et al.
patent: 4512030 (1985-04-01), Fukuta
patent: 4882505 (1989-11-01), Furman

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