Counter-bias scheme to reduce charge gain in an electrically era

Details Counter-bias scheme to reduce charge gain in an electrically era Counter-bias scheme to reduce charge gain in an electrically era

1997-12-29

1999-09-28

Hoang, Huan

Static information storage and retrieval

Floating gate

Particular biasing

36518501, 36518505, G11C 1604

Patent

active

059598891

ABSTRACT:
A counter-bias scheme to reduce or eliminate charge gain in a single-poly or double-poly electrically erasable (E.sup.2) cell having separate program and read transistors which may be configured as a 6-wire cell includes applying a counter-bias voltage to the drain of a program select transistor of the E.sup.2 cell during a read operation. The counter-bias voltage may be approximately equal to a voltage on the floating gate of the cell during the read operation. The present scheme reduces the threshold voltage shifts which may otherwise be experienced in the cell during continuous read operations. In particular, the counter-bias voltage acts to reduce the electric field across the tunnel oxide of the program select transistor, thus reducing the charge gain on the floating gate.

REFERENCES:
patent: 5101378 (1992-03-01), Radji et al.
patent: 5331590 (1994-07-01), Josephson et al.
patent: 5359573 (1994-10-01), Wang
patent: 5742542 (1998-04-01), Lin et al.
patent: 5748525 (1998-05-01), Wong et al.

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