Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Pulse multiplication or division
Reexamination Certificate
2006-11-21
2006-11-21
Lam, Tuan T. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Pulse multiplication or division
C327S107000, C327S299000
Reexamination Certificate
active
07139361
ABSTRACT:
Digital frequency synthesizer (DFS) circuits and methods use counters to define the positions of the output clock edges. A clock divider divides an input clock by a positive integer to provide a divided clock. A first counter circuit counts for one divided clock period, and the count is provided to a timing circuit that generates two or more sets of intermediate values. Each set represents a set of intermediate points within a period of the divided clock. Based on a specified multiplication value, one set of intermediate values is selected. Utilizing the divided clock, the selected set of intermediate values, and a second counter running at the same frequency as the first counter circuit, an output clock generator provides an output clock having an initial pulse at the beginning of each divided clock period, and a subsequent pulse at intermediate points represented by the selected set of intermediate values.
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Cartier Lois D.
Xilinx , Inc.
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