Counter-based clock multiplier circuits and methods

Details Counter-based clock multiplier circuits and methods Counter-based clock multiplier circuits and methods

2005-06-14

2005-06-14

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S291000, C377S047000

Reexamination Certificate

active

06906562

ABSTRACT:
Clock multiplier circuits and methods use counters to define the positions of the output clock edges. A plurality of counters are each clocked by a count clock relatively much faster than the input clock. A first counter counts for one input clock period, and the counted value is stored. The stored value is then divided and added to provide the number of counts in various fractions of the input clock period. The divided and/or added values are provided to a second counter that counts from zero and generates various pulses at desired times throughout the input clock period. The pulses from the second counter are used (sometimes in combination with the input clock signal) to provide output clock edges at predetermined times during the input clock cycle.

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patent: 6788120 (2004-09-01), Nguyen

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