Counter-address memory for multi-channel timing signals

Details Counter-address memory for multi-channel timing signals Counter-address memory for multi-channel timing signals

1983-06-07

1985-11-12

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307269, 307597, 307602, 328 62, 328 72, 377 51, 377114, H03L 724

Patent

active

045531005

ABSTRACT:
A counter counts clock signals following a reference signal to provide an address for accessing a memory wherein marks are stored at respective addresses corresponding to desired timing signals with respect to the reference signal. The memory has plural channels, all of which are accessed by the same count value, to provide different timing signals on different channel outputs corresponding to the marks stored in respective portions of the memory. Different sets of timing signals can be stored in different memory blocks, and the memory block which is accessed by the count value can be selected. The memory can be divided into plural memories of smaller capacity, and low speed memories can be used. A timing signal with respect to a first reference signal can be provided after the occurrence of the subsequent reference signal. The marks that are stored in the memory can be quickly erased and the next set of marks put into the memory, including offset data for compensated timing signals for rapid testing of devices.

REFERENCES:
patent: 3508207 (1970-04-01), Shigaki
patent: 4122309 (1978-10-01), Jacobsen
patent: 4291241 (1981-09-01), Mayama et al.
patent: 4385395 (1983-05-01), Tanaka et al.
patent: 4413350 (1983-11-01), Bond et al.
patent: 4415861 (1983-11-01), Palmquist et al.
patent: 4431926 (1984-02-01), Mayumi
patent: 4468624 (1984-08-01), Rehbein et al.

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