Counter

Boots – shoes – and leggings

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377 26, G06M 300

Patent

active

052315924

ABSTRACT:
A counter has an electrically erasable and programmable read-only memory (EEPROM), a write circuit, and a read circuit. The EEPROM, which can be rewritten at least V times, is divided into count areas M.sub.O, . . . , M.sub.N each capable of storing count values from zero to V, and a number area for storing a number K from zero to N identifying the count area currently in use. The write circuit uses the count areas M.sub.O, . . . , M.sub.N in succession to store counts as high as N.times.V. The read circuit obtains the current count value by reading K from the number area, reading the contents C of the Kth count area M.sub.K, and calculating C+(V.times.K).

REFERENCES:
patent: 4774544 (1988-09-01), Tsuchiya et al.
patent: 4885943 (1989-12-01), Tottell et al.
patent: 5023813 (1991-06-01), Brown, III
patent: 5103409 (1992-04-01), Shimizu et al.

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