Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Counter includes circuit for performing an arithmetic function
Patent
1988-02-29
1989-06-06
Heyman, John S.
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Counter includes circuit for performing an arithmetic function
377 51, 3647462, 364770, G06F 750
Patent
active
048377910
ABSTRACT:
A high-speed counter using radix-N Signed-Digit redundancy adders, an initial value generator and an interim value generator for each digit. The initial value is selected based upon a desired count. The transfer digit and interim value for each digit are generated to eliminate a carry propagation from a lower digit position. The high-speed counter reaches a desired count with a certain delay time regardless of the starting count value.
REFERENCES:
patent: 3375358 (1968-03-01), Franck
patent: 3462589 (1969-08-01), Robertson
patent: 3946219 (1976-03-01), Lucas
patent: 4400615 (1983-08-01), Asami et al.
patent: 4623982 (1986-11-01), Ware
patent: 4700325 (1987-10-01), Ware
patent: 4751631 (1988-06-01), Fisher
The Transactions of the IECE of Japan, vol. E 69, No. 4, Apr. 1986, pp. 261/263, T. Nakanishi et al. "CMOS Radix-2 Signed-Digit Adder by Binary Code Representation".
"Binary-Compatible Signed-Digit Arithmetic" by Aulzienis, Proceedings-Fall Joint Computer Conf. 1964, pp. 663-672.
Nakanishi Tadashi
Yamauchi Hironori
Heyman John S.
Nippon Telegraph and Telephone Corporation
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