Cost efficient nonvolatile SRAM cell

Details Cost efficient nonvolatile SRAM cell Cost efficient nonvolatile SRAM cell

2007-11-27

2007-11-27

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185050

Reexamination Certificate

active

10990173

ABSTRACT:
A cost efficient nonvolatile memory cell may include an inverter, an access gate coupled to the inverter for controlling access to the memory cell, and a control gate. The inverter may include a floating gate at an input of the inverter, the floating gate formed in a first polysilicon layer, and a tunnel window formed in a tunnel oxide area, wherein the tunnel oxide area is covered by at least a portion of the floating gate. The control gate may control charge on the floating gate, and may be formed in a second polysilicon layer, wherein the second polysilicon layer is above the first polysilicon layer.

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