Correlator and delay lock loop circuit

Pulse or digital communications – Spread spectrum – Direct sequence

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C375S147000, C375S150000

Reexamination Certificate

active

06650689

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention is directed to a correlator and a delay locked loop circuit. More particularly, to a correlator for detecting the code phase of a spreading code on the transmitting side (i.e., the code phase of the received spreading code) in a case where a direct-sequence spread-spectrum signal is received, and to a delay locked loop (DLL) circuit for maintaining the synchronization between the received spreading code and a reference spreading code.
Direct-sequence code division multiple-access based upon direct-sequence spread-spectrum (DS-SS) modulation has been considered as a wireless access scheme for next-generation digital mobile communications systems. In order to receive a spread-spectrum signal, the code phase of the spreading code on the transmitting side must be detected on the receiving side and a spreading code for despreading purposes must be generated so as to achieve phase synchronization with the spreading code on the transmitting side.
Digital cellular wireless communication systems using DS-CDMA (Direct-Sequence Code Division Multiple-Access) technology have been developed as next-generation mobile communication systems for implementing wireless multimedia communications. In a CDMA digital cellular wireless communications system of this kind, a base station transmits control information and user information after multiplying this information with a spreading code. Individual mobile stations spread and transmit information using a spreading code specified by the base station. In order for a mobile station to correctly receive information such as control information from the base station in a CDMA digital cellular wireless communications system of this kind, it is necessary to identify the timing at which the spread-spectrum modulation starts at the base station, i.e., the phase of the spreading code.
FIG. 19
shows a receiver of a mobile station for a CDMA digital cellular wireless communication system. The receiver includes an antenna
1
, a receiver circuit
2
for performing amplification and frequency conversion from RF (radio frequency) to IF (intermediate frequency), a QPSK detector
3
for performing QPSK detection and outputting I, Q signals and an AID converter
4
for converting baseband analog I, Q signals output from detector
3
to digital I, Q data, a despreading circuit
5
for applying despread processing to the I, Q data output by the A/D converter
4
, a data demodulator
6
for performing synchronous detection, data discrimination and error correction, a correlator
7
for performing a correlation operation in order to identify spread start timing (the phase of the received spreading code) and a timing decision unit
8
for identifying spread start timing (phase) from correlation value.
The correlator
7
performs a correlation operation between a received spread-spectrum data sequence and a reference spreading code sequence (a spreading code sequence identical with that on the side of the base station).
As shown in
FIG. 20
, a spreader
9
on a transmitting side executes spread processing and transmits a signal indicated by:
X
(
t
)=
a
(
t

c
(
t
)
Where a(t) represents transmitted data and c(t) a PN (pseudorandom number) sequence.
The PN sequence c(t) is a spreading code sequence of “1”s and “0”s. The same code sequence (a code sequence of N chips) is repeated on a per-symbol basis, wherein one symbol corresponds to one-bit of data.
The signal x(t) is received on the receiving side, where the correlator
7
calculates the correlation between the signal x(t) and a reference spreading code c(t−&tgr;) and outputs a correlation value R(t) indicated by the following equation:
R
(
t
)=&Sgr;
x
(
t

c
(
t
−&tgr;)
=&Sgr;
a
(
t

c
(
t

c
(
t
−&tgr;),
t=Tc
, 2
Tc, . . . N·Tc
where &tgr; represents a code shift (phase difference) between the spreading code on the transmitting side and the reference spreading code of the correlator on the receiving side. The integration interval is the duration of one symbol (the time period of N chips, which is equal to N·Tc).
If “a(t)=1” holds in the above equation, the correlation value R(t) will indicate the auto correlation value of the PN sequence. If the PN sequence is an M sequence, R(t)=N (1 when normalized) is obtained as a maximum at &tgr;=0 and R(t)=1/N holds at &tgr;≠0. In actuality, a(t) is unknown and may be “1” or “0”. However, by assuming for example that “1”=−1 and “0”1, and integrating the absolute value of a(t)·c(t)·c(t−&tgr;), R(t)=1 is obtained at &tgr;=0 and R(t)=1/N at &tgr;≠0.
Thus, by calculating correlation values while changing the phase of the reference spreading code c(t−&tgr;) one chip width Tc at a time and detecting the timing at which the correlation value exceeds a set level, it is possible to identify the spread start timing on the transmitting side (the phase of the spreading code on the transmitting side). Accordingly, the timing decision unit
8
of
FIG. 19
acquires the spread start timing (phase) based upon the timing at which the correlation value output by the correlator
7
exceeds the set level and inputs this timing to the despreader circuit
5
.
A matched filter and a sliding correlator are available as the principal correlation detection techniques applied to DS-SS signals.
FIG. 21
shows a matched filter
71
. The matched filter includes an N-chip shift register (s
1
-s
N
)
71
a
for successively shifting the received spread-spectrum data sequence of the baseband (the output of the A/D converter in
FIG. 19
) at the chip frequency. Also included is an N-chip shift register (c
1
-c
N
)
71
b
for storing the reference spreading code sequence, N-number of multiplying corresponding bits of the baseband spread-spectrum data sequence and reference spreading code sequence. An adder circuit
71
d
is further included for adding the outputs of the multipliers and a PN generator
71
e
for generating the PN sequence (the reference spreading code sequence).
The reference spreading code sequence is composed of N chips. The matched filter
71
outputs one correlation value R(t) per chip period Tc and then successively outputs a correlation value every time the phase of the baseband spread-spectrum data sequence changes by one chip width Tc. The matched filter thus outputs correlation values of N-number of different phases over the period of one symbol.
The timing decision unit
8
monitors the correlation value R(t) output by the matched filter
71
, determines whether the correlation value has exceeded the set level and identifies the start of the spreading code sequence on the transmitting side (spread start timing) when the correlation value exceeds the set level.
FIG. 22
shows a sliding correlator
72
, which includes a PN generator
72
a
for generating a PN sequence (reference spreading code sequence). The reference spreading code sequence is composed of N chips and is generated cyclically at the symbol period T (=N×Tc). Further, multiplier
72
b
multiples the baseband spread-spectrum data sequence (the received signal) by the reference spreading code sequence chip by chip and outputs the result.
An integrator
72
c
integrates N chips of the output of multiplier
72
b
and outputs the correlation value R(t). The integrator
72
c
includes an adder
73
for adding the output of the multiplier
72
b
and the current integrated value, and a delay circuit
74
for outputting the integrated value from adder
73
upon delaying the value by one chip period.
The sliding correlator
72
outputs one correlation value R(t) in one symbol period (the period of N chips) and shifts the phase of the reference spreading code by one chip every symbol, thereby outputting correlation values of N-number of different phases over the period of N symbols (=N
2
·Tc).
The timing decision unit
8
monitors the correlation value R(t) output by the sliding correlator
72
to determine whether the correlation v

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Correlator and delay lock loop circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Correlator and delay lock loop circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Correlator and delay lock loop circuit will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3163956

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.