Electrical computers: arithmetic processing and calculating – Electrical hybrid calculating computer – Particular function performed
Reexamination Certificate
2001-03-06
2004-12-07
Mai, Tan V. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical hybrid calculating computer
Particular function performed
Reexamination Certificate
active
06829625
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a device for calculating the correlation value of compared vectors. The correlation value calculating device according to the present invention is used, for example, in a CDMA communications system.
2. Description of Related Art
A correlation value calculating device is a device for calculating the correlation value of compared vectors. These vectors are respectively constituted by a plurality of components. The correlation value calculating device respectively calculates the absolute values of the differences between corresponding components of the vectors. The correlation value calculating device then calculates the sum of these absolute values. This sum is the correlation value.
Previously known correlation value calculating devices include those disclosed in the following references, for example.
Reference I : T. Shibata et. al., “Advances in Neuron-MOS Application”, ISSCC Digest of Technical Papers, pp. 304-305, Feb. 10, 1996
Reference II : T. Ohmi et. al., “Association Hardware for Intelligent Electric Systems”, Papers of The Institute of Electronics, Information and Communication Engineers, D-I Vol. J81-D-I No.2, pp. 51-61, February 1998
Reference III: M. Konda et. al., “Memory-Merged Matching Cell”, Proceedings of the 6
th
International Conference on Microelectronics for Neural Networks, Evolutionary & Fuzzy Systems (MicroNeuro '97), pp. 175-180, September, 1997
Reference IV: A. Okada et. al., “A NEURON-MOS Parallel ASSOCIATOR FOR HIGH SPEED CDMA MATCHED FILTER”, 1999 IEEE International Symposium on Circuit and Systems (ISCAS 99)
The correlation value calculating devices in references I-III respectively compare one input vector with a plurality of template vectors, in a simultaneous fashion. These correlation value calculating devices comprise a plurality of calculator devices, called “associators”, and a single large-capacity memory. Firstly, a plurality of template vectors stored in the large-capacity memory are downloaded into the associators. Each component of the respective template vectors is stored respectively in a single corresponding associator. Thereupon, the correlation value calculating devices receive an input vector. The various components of the input vector are input to the corresponding plurality of associators. Each associator calculates the absolute value of the difference between the two components input thereto. The sum of these absolute values is calculated for each template vector, and then output from the correlation value calculating device.
The correlation value calculating devices in references I-III are provided with a number of associators corresponding to the number of components, in other words, the number of dimensions, of each template vector. Each associator respectively comprises 13 transistors. Therefore, if the number of template vectors is high, and the number of dimensions of the template vectors is high, then the circuitry of the correlation value calculating devices will become very large in scale. Furthermore, in the correlation value calculating devices in references I-III, it is necessary to provide wiring from the large-capacity memory to the associators, in order to download the template vectors. This wiring also causes the circuitry of the correlation value calculating devices to increase in size. In addition, if the number of template vectors is high and the number of template vector dimensions is high, then the time required for downloading will be long, and hence processing time will also be long.
The correlation value calculating device according to reference IV comprises associators wherein the components of the template vectors are stored previously. Therefore, this type of correlation value calculating device does not require a large-scale memory or wiring for download purposes. Furthermore, the associators in this correlation value calculating device only have two transistors. Therefore, the scale of the circuitry in this correlation value calculating device is small. However, with this correlation value calculating device, it is difficult to rewrite the template vectors.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a correlation value calculating device having circuitry of a small scale, which enables rewriting of template vectors.
Therefore, the correlation value calculating device relating to the present invention comprises: one or a plurality of bit lines; a plurality of word lines disposed in such a manner that they intersect with the bit lines; a plurality of memory cells disposed at the intersection points of the bit lines and the word lines, respectively comprising a capacitor for storing a binary value according to the terminal-to-terminal voltage thereof, and a transistor for controlling connection and disconnection between one terminal of the capacitor and the bit line, in accordance with the electric potential of the word line; a word line driver for inputting an input vector component to each word line pair constituted by two adjacently positioned word lines, applying a high-level electric potential to the one word line and applying a low-level electric potential to the other word line, if the component is a first value, or applying a low-level electric potential to the one word line and applying a high-level electric potential to the other word line, if the component is a second value; and a sense amplifier for amplifying and outputting the electric potential of the bit lines.
The correlation value calculating device relating to the present invention has a simple composition of memory cells. Furthermore, the correlation value calculating device relating to the present invention writes values to capacitor, and hence rewriting can be performed readily.
REFERENCES:
patent: 3830965 (1974-08-01), Beaudette
patent: 5784017 (1998-07-01), Craven
T. Shibata et al., “Advances in Neuron-MOS Application” ISSCC Digest of Technical Papers, pp. 304-305, Feb. 10, 1996.
T. Ohmi et al., “Association Hardware for Intelligent Electric Systems” Papers of the Institute, Information and Communication Engineers, D-I vol. 1 J81-D-I No. 2, pp. 51-61, Feb. 1998.
M. Konda et al., “Memory-Merged Matching Cell” Proceedings of the 6thInternational Conference on Microelectronics for Neutral Networks, Evolutionary & Fuzzy Systems (MicroNeuro '97), pp. 175-180, Sep. 1997.
A. Okada et al., “A Neuron-MOS Parallel Associator for High Speed CDMA Matched Filter”, 1999 IEEE International Symposium on Circuit and Systems (ISCAS 99).
Mai Tan V.
Oki Electric Industry Co. Ltd.
Volentine Francos & Whitt PLLC
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