Correlation detector and communication apparatus

Details Correlation detector and communication apparatus Correlation detector and communication apparatus

1995-06-13

1997-06-10

Chin, Wellington

Multiplex communications

Communication over free space

Combining or distributing information via code word channels...

375206, 375208, 370350, H04J 1300

Patent

active

056383622

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention relates to a correlation detector of a radio receiver in a CDMA (Code Division Multiple Access) system which carries out multiple access by using a spread spectrum in mobile communications.
In particular, the present invention relates to a CDMA synchronizing circuit that synchronizes a spreading code for despreading the received signal to a spreading code in a received signal in CDMA communications.


BACKGROUND ART

CDMA communications perform multiple access propagation by spreading information into wideband signals using spreading codes with rates higher than the rate of the information, and are roughly divided into direct sequence (DS) systems that spread modulated signals by high rate spreading codes, and frequency hopping (FH) systems. The FH system resolves each symbol into smaller elements called chips, and translates the chips into signals with different center frequency at a high speed. Since the implementation of the FH system is difficult, the DS system is generally used. The DS system recovers the original narrowband signal by despreading the wideband received input signal at a receiving end, followed by demodulation. In the despreading process, correlation detection is performed between the spreading code included in the received signal and a spreading code generated at the receiving end.
Thus, the receiver for receiving the spread signal in the DS system is usually provided with a replica (reference PN sequence) of the PN sequence (received PN sequence) in the received signal, and establishes synchronization between the reference PN sequence and the received PN sequence. FIG. 1 shows a conventional synchronization circuit using a matched filter. The received signal applied to an input terminal 10 is supplied to a memory circuit 11 with taps. The number of taps of the tapped memory circuit 11 is the same as the number of chips in a spreading code interval (that is, a processing gain PG). The outputs of the taps of the memory circuit 11 are multiplied by the reference spreading code stored in a tap coefficient circuit 13 by multipliers 12. The resultant products are summed by an integrator 14, which outputs the sum from its output terminal 16 as a correlation value 15.
Using the matched filter makes it possible to quickly establish the synchronization because the peaks of the correlation value appear at the same interval as that of the spreading code. However, since the capacity of the tapped memory circuit 11 and the number of the multipliers 12 increase in proportion to the processing gain, the power consumption of the receiver will increase with the interval of the spreading code. Therefore, the conventional synchronizing circuit is not appropriate for portable devices or mobile devices.
Using a sliding correlation detector as shown in FIG. 2 makes possible power saving and downsizing of the circuit. In FIG. 2, a received signal 21 inputted to the input terminal 10 is multiplied by a spreading code, which is generated by a spreading code replica generator 30, by a multiplier 22 to obtain the correlation between the two. The resultant product is passed through a bandpass filter (BPF) 23, followed by peak power detection by a square-law detector 24. The detected power is integrated over a fixed time (normally, .+-. one chip interval) by an integral-dump circuit 25. The integrated result is compared with a threshold value by a threshold value decision circuit 26 which decides that initial acquisition has been completed if the integrated result exceeds the threshold value, and proceeds to the next step (tracking mode). If the integrated result is less than the threshold value, the decision circuit 26 supplies a control voltage 28 to a voltage controlled clock generator (VCCG) 29 which slides the phase of the replica so that the phase of the spreading code generated by the spreading code replica generator 30 is shifted by 1/N chip interval (N is a natural number equal to or greater than one). The initial acquisition has been completed by repeating the proce

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Richard A. Yost & Robert W. Boyd, "A Modified PN Code Tracking Loop: Its Performance Analysis and Comparative Evaluation" IEEE, Transactions, vol. COM-30, No. 5, May 1982, Left col., p. 1027 to left col., p. 1028, Figs. 1(a), 2.
Masao Nakagawa "Basic and Application of Spread Spectrum Communication Technology", Torikeps K.K., Mar. 13, 1987, Lines 27 to 2, p. 77, Lines 1 to 6, p. 78, Figs. 10, 12.
Kazumasa Nitta and two others "Method of Constituting UW Reverse Modulation AFC and characteristics" 1993 IEICE Autumn General Conference Lecture Thesis, vol. 2 thesis No. B330, pp. 2 to 330, Sep. 5, 1993, Lines 12 to 25, (1) Premodulation UW Detection Circuit, Fig. 1.
Masao Nakagawa "Basic and Application of Spread Spectrum Communication Technology", Torikeps K.K., Mar. 13, 1987, Lines 1 to 17, p. 92, Fig. 28.

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