Pulse or digital communications – Receivers – Particular pulse demodulator or detector
Reexamination Certificate
1998-09-29
2002-02-05
Pham, Chi (Department: 2731)
Pulse or digital communications
Receivers
Particular pulse demodulator or detector
C375S152000
Reexamination Certificate
active
06345077
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for detecting a correlation between digital signals using a spectrum communication system for pocket telephones and a matched filter unit that uses the correlation detecting method.
2. Description of the Related Art
At first, a configuration of a related art matched filter unit will be described with reference to FIG.
16
.
FIG. 16
shows a configuration of the first related art matched filter unit used for receiving signals from two 5-time diffusion 5-tap channels, each composed of an FIR digital filter.
This related art matched filter unit is provided with input terminals
1
and
2
, a clock signal input terminal
3
, a shift register
9
composed of five delay circuits
4
to
8
disposed in five stages, a shift register
15
composed of five delay circuits
10
to
14
disposed in five stages, multipliers
16
to
25
, adders
26
and
27
, and output terminals
28
and
29
. Each of the multipliers
16
to
20
uses corresponding one of the code values in a back-diffusion code string C4C3C2C1C0 for the digital signal I. Each of the multipliers
21
to
25
uses corresponding one of the code values in a back-diffusion code string C04C03C02C01C00 for the digital signal Q.
This related art matched filter unit provides each channel with a correlation detecting circuit. Since the matched filter unit has two channels, it is provided with two matched filters
30
and
31
. The matched filter
30
corresponding to the digital signal I is provided with a shift register
9
composed of five delay circuits
4
to
8
disposed in five stages, multipliers
16
to
20
, and an adder
26
. In the same way, the matched filter
31
corresponding to the digital signal Q is provided with a shift register
15
composed of five delay circuits
10
to
14
disposed in five stages, multipliers
21
to
25
, and an adder
27
.
The input terminals
1
and
2
receive the digital signals I and Q obtained by sampling analog signals (for example, spectrum diffusion signals) with a 4.096 MHz sampling frequency. The digital signals I and Q are synchronized with a 4.096 MHz clock signal CLK entered to the clock signal input terminal. The digital signal I is entered to the first delay circuit
4
of the shift register
9
, then shifted from the first delay circuit
4
to the fifth delay circuit
8
sequentially in synchronization with the clock signal CLK. In the same way, the digital signal Q is entered to the first delay circuit
10
of the shift register
15
, then shifted from the first delay circuit
10
to the fifth delay circuit
14
sequentially in synchronization with the clock signal CLK.
The multiplier
16
multiplies a signal output from the first delay circuit
4
of the shift register
9
by the back-diffusion code value C0 of the back-diffusion code string C4C3C2C1C0. Each of the multipliers
17
to
20
multiplies a signal output from corresponding one of the delay circuits
5
to
8
by corresponding one of the back-diffusion code values C1 to C4. Each of the multipliers
21
to
25
multiplies a signal output from corresponding one of the delay circuits
10
to
14
by corresponding one of the back-diffusion code values C00 to C04.
The adder
26
receives and adds the result of multiplication performed in each of the multipliers
16
to
20
, while the adder
27
receives and adds the result of multiplication performed in each of the multipliers
21
to
25
. Consequently, a value of the correlation with the entered digital signal I is output to the output terminal
28
and a value of correlation with the entered digital signal Q is output to the output terminal
29
.
Next, description will be made for a procedure of multiplication performed in each of the multipliers
16
to
25
, as well as a procedure of back-diffusion computing performed in each of the adders
26
and
27
with reference to the timing chart shown in FIG.
17
.
In the initial state, all the signals output from the delay circuits
4
to
8
and
10
to
14
composing the shift registers
9
and
15
respectively are set in the low level.
At first, in the first operation state of the matched filter
30
, the first sampling data D0 of the digital signal I is entered to the input terminal
1
synchronously with the clock signal CLK, then fetched into the first delay circuit
4
. The multiplier
16
multiplies this sampling data D0 by the back-diffusion code value C0. Consequently, the multiplier
16
outputs a signal indicating the value D0×C0.
In the second operation state, the second sampling data D1 of the digital signal I is entered to the input terminal
1
synchronously with the clock signal CLK, then fetched into the first delay circuit
4
. At the same time, the first sampling data D0 is fetched into the second delay circuit
5
. Consequently, the multiplier
16
multiplies the second sampling data D1 by the back-diffusion code value C0 and the multiplier
17
multiplies the first sampling data D0 by the back-diffusion code value C1. The multiplier
16
thus outputs a signal indicating the value D1×C0 and the multiplier
17
outputs a signal indicating the value D0×C1. Hereafter, the same processings are repeated until the fourth sampling data D3 is entered to the input terminal
1
.
After this, if the fifth sampling data D4 of the digital signal I is entered to the input terminal
1
synchronously with the clock signal CLK entered to the clock signal input terminal
3
, the first to fifth sampling data D0 to D4 are fetched into the delay circuits
4
to
8
respectively. Consequently, the multiplier
16
outputs the result of multiplication indicating the value D4×C0 and the multiplier
17
outputs the result of multiplication indicating the value D3×C1. And, the multiplier
18
outputs the result of multiplication indicating the value D2×C2, the multiplier
19
outputs the result of multiplication indicating the value D1×C3, and the multiplier
20
outputs the result of multiplication indicating the value D0×C4. This completes all the necessary processings for finding a correlation value between the back-diffusion code string C4C3C2C1C0 and the first five sampling data D0 to D4 of the digital signal I. The adder
26
adds the multiplication result from each of the multipliers
16
to
20
and outputs the correlation result H (4) from the output terminal
28
.
The same processings are also performed in the matched filter
31
. The first five sampling data D00 to D04 of the digital signal Q are entered to the input terminal
2
. Each of the multipliers
21
to
25
, as well as the adder
27
performs a back-diffusion computing processing with respect to the back-diffusion code string C04C03C02C01C00 and the correlation result H (04) is output from the output terminal
29
. Hereafter, the same processings are repeated.
Next, description will be made for another related art matched filter unit used when a received signal is over-sampled.
When a receiving timing of a received signal is detected by detecting the correlation with the received signal for a pocket telephone, the received signal is usually over-sampled by m times with respect to the chip rate frequency, then it is entered to a matched filter unit. This is to improve the accuracy of detecting the receiving timing.
FIG. 18
is a configuration of the second related art 5-time diffusion 10-tap matched filter unit composed of FIR digital filters.
This related art matched filter unit is provided with input terminals
101
and
102
, a clock signal input terminal
103
, a shift register
109
composed of delay circuits
104
to
108
disposed in five stages, a shift register
115
composed of delay circuits
110
to
114
disposed in
10
stages, multipliers
116
to
125
, adders
126
and
127
, and output terminals
128
and
129
. Each of the multipliers
116
to
120
uses corresponding one of the code values of the back-diffusion code string C4C3C2C1C0 for the digital signal I, while each of the multipliers
1
Pham Chi
Stevens Davis Miller & Mosher LLP
Tran Khai
LandOfFree
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