Correlation detecting circuit operable in a low frequency

Pulse or digital communications – Repeaters – Testing

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375106, H04B 318

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active

049088386

ABSTRACT:
In an adaptive equalizer system for equalizing, in response to a plurality of controllable tap gains, a received signal carrying a transmission data sequence digitized by a reference clock signal, a correlation detecting circuit (63') comprises a divider (111) for frequency dividing a reproduced clock signal representative of a reproduction of the reference clock signal to produce a divided clock signal. A serial-parallel converter (120) is for converting a reproduced data sequence representative of a reproduction of the transmission data sequence and a digital error signal relative to the reproduced data sequence into a plurality of converted data sequences and a plurality of converted error signals in synchronism the divided clock signal. As Exclusive logic circuit (70) is for carrying out an exclusive logic operation on the converted error signals and the converted data sequences to produce a plurality of correlation signals which are collectively used in controlling the controllable tap gains.

REFERENCES:
patent: 4453256 (1984-06-01), Ryu
patent: 4475211 (1984-10-01), Mattis, Jr. et al.
patent: 4809298 (1989-02-01), Sakane et al.

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