Pulse or digital communications – Repeaters – Testing
Patent
1991-01-15
1994-01-04
Kuntz, Curtis
Pulse or digital communications
Repeaters
Testing
375 18, 375 94, 375116, H04B 1404
Patent
active
052767094
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a transmission system using correlation codes, and more particularly to a method for generating data to be transmitted as well as receiving data and to a configuration of an apparatus that performs such operations.
BACKGROUND ART
In prior art transmission systems using the correlation code, a specific coding rule is introduced that governs a plurality of adjoining input data to narrow the band width of an output signal.
For example, in a system with a bit rate of f.sub.0, a secondary bipolar (modified duobinary) code, disclosed in a literature entitled "Advance in PCM Communication" (Sanpo) by Inose and Miyagawa at page 89, has a main lobe of less than f.sub.0 /2 and its band is one fourth that of the ordinary non-return-to-zero (NRZ) code.
In a transmission system using the correlation code, the output at a certain time is determined by a combination of a present input as well as past inputs, so that it is difficult to fix a frame synchronization pattern. For this reason, a new frame synchronization method was proposed in the Japanese Patent Laid-Open No. 119947/1984 "Partial Response Transmission Method." This method establishes the frame synchronization by deliberately inserting a code violation pattern although the frame synchronization pattern is not fixed.
With the above prior art (Japanese Patent Laid-Open No. 119947/1984), while the frame synchronization becomes possible, the frame synchronization pattern varies from one frame to another because the pattern at the transmitter depends on the past inputs. Therefore, no fixed frame synchronization patterns can be observed on the transmission line. Another problem is that when a precoder, described at page 83 of the above reference "Advance in PCM Communication," is used, not only does the dependence of the output of the coder on all the past data make it impossible to fix the frame synchronization pattern, but also bit errors that occurred in the precoder circuit affect the data at succeeding stages. Therefore, it is necessary to suppress this error propagation.
SUMMARY OF THE INVENTION
The object of this invention is to provide a transmission system which fixes the frame synchronization pattern on the transmission line and thereby makes the observation of the transmitted data easy.
To make the frame synchronization pattern constant on the transmission line, this invention resets or presets registers, which make up the coder, in each frame period, as detailed later. However, resetting or presetting the registers in the coder for each frame period results in a complete loss of past recorded data and thus may cause a code violation. In the event of such code violation, the receiver cannot perform correct decoding. To prevent decoding error also requires resetting a Viterbi decoder, and this complicates the construction of the receiver.
Another object of this invention is to provide a transmission system which can fix the frame synchronization pattern without generating a code violation or facilitating the observation of transmitted data.
DISCLOSURE OF THE INVENTION
To achieve the above objective, this invention provides a means to reset or preset a group of registers built into the coder in the transmitter for each frame of a fixed interval. It also provides a means to bypass the frame synchronization signal, with the contents of the registers kept intact.
Now, by referring to FIGS. 1 and 2, these means will be described.
FIG. 1 shows the configuration of the coder.
The coder consists of: registers 41 to 43; constant multiplier 31 to 33; modulo-2 adders 21 to 23; adders 61 to 63; a selector 1 and an inverter 50. A means for fixing the output signal is realized by sending a reset or preset signal 7 inverted by the inverter 50 to reset or preset terminals 71 to 73 of the registers 41 to 43.
FIG. 2 shows the configuration of another coder, which consists of: a selector 11 to select between an output of the modulo adder 22 and a zero input 5; another selector 12 to choose between the adder 62 and th
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Kazawa Tohru
Mass'e Ichiro
Miyamoto Takanori
Morita Takashi
Suzuki Toshiro
Hitachi , Ltd.
Kuntz Curtis
Vo Don N.
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