Correlating an inline parameter to a device operation parameter

Details Correlating an inline parameter to a device operation parameter Correlating an inline parameter to a device operation parameter

2002-09-25

2004-10-26

Shechtman, Sean (Department: 2125)

Data processing: generic control systems or specific application

Specific application, apparatus or process

Product assembly or manufacturing

C700S121000, C700S033000, C700S044000, C702S084000

Reexamination Certificate

active

06810296

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor manufacturing, and, more particularly, to a method and apparatus for a modeling inline parameters to a device operation parameter relating to a device.
2. Description of the Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today's manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and therefore, require a number of inputs that are generally fine-tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Generally, a set of processing steps is performed across a group of semiconductor wafers, sometimes referred to as a lot. For example, a process layer that may be composed of a variety of different materials may be formed across a semiconductor wafer. Thereafter, a patterned layer of photoresist may be formed across the process layer using known photolithography techniques. Typically, an etch process is then performed across the process layer using the patterned layer of photoresist as a mask. This etching process results in the formation of various features or objects in the process layer. Such features may be used as, for example, a gate electrode structure for transistors. Many times, trench isolation structures are also formed across the substrate of the semiconductor wafer to isolate electrical areas across a semiconductor wafer. One example of an isolation structure that can be used is a shallow trench isolation (STI) structure.
The manufacturing tools within a semiconductor manufacturing facility typically communicate with a manufacturing framework or a network of processing modules. Each manufacturing tool is generally connected to an equipment interface. The equipment interface is connected to a machine interface to which a manufacturing network is connected, thereby facilitating communications between the manufacturing tool and the manufacturing framework. The machine interface can generally be part of an advanced process control (APC) system. The APC system initiates a control script, which can be a software program that automatically retrieves the data needed to execute a manufacturing process.
FIG. 1
illustrates a typical semiconductor wafer
105
. The semiconductor wafer
105
typically includes a plurality of individual semiconductor die
103
arranged in a grid
150
. Using known photolithography processes and equipment, a patterned layer of photoresist may be formed across one or more process layers that are to be patterned. As part of the photolithography process, an exposure process is typically performed by a stepper on approximately one to four die
103
locations at a time, depending on the specific photomask employed. The patterned photoresist layer can be used as a mask during etching processes, wet or dry, performed on the underlying layer or layers of material, e.g., a layer of polysilicon, metal or insulating material, to transfer the desired pattern to the underlying layer. The patterned layer of photoresist is comprised of a plurality of features, e.g., line-type features or opening-type features that are to be replicated in an underlying process layer.
Turning now to
FIG. 2
, a typical flow of processes performed on a semiconductor wafer
105
by a semiconductor manufacturing system is illustrated. Generally, semiconductor wafers
105
are processed based upon a predetermined process flow by a manufacturing system (block
210
). Upon processing at least one semiconductor wafers
105
, metrology data is generally acquired (block
220
). Upon acquiring the metrology data, the manufacturing system may perform a metrology data analysis function to analyze errors that may occur on the processed semiconductor wafers
105
(block
230
). Based upon the metrology data analysis, the manufacturing system may perform adjustments to processing operations performed by the manufacturing system (block
240
).
Utilizing the prior art process flow implemented by current manufacturing systems, a lot of semiconductor wafers
105
may be processed through several process steps without a substantial focus on the performance characteristics of devices produced from the processed semiconductor wafers
105
. In other words, a lot of semiconductor wafers
105
may be pushed through a string of manufacturing processes based on available data, without an adequate focus on several device operation parameters relating to devices produced from the processed semiconductor wafers
105
. For example, the data access time, such as erase time, relating to a memory device may be affected by the processing flow of a process flow of semiconductor wafers
105
. The operation of a logic device, such as a memory device may be greatly affected by several inline processing operations. Without an adequate focus on how one or more inline parameters may affect device operation, efficient production of devices made from the semiconductor wafers
105
may be adversely affected.
The present invention is directed to overcoming, or at least reducing, the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method is provided for correlating an inline parameter to a device operation parameter of a device. Inline parameter data relating to a processed workpiece is received. A determination is made whether the inline parameter would result in a value of a device operation parameter within a predetermined range. At least one process operation performed upon the workpiece is adjusted in response to a determination that the inline parameter would not result in a value of the device operation parameter within a predetermined range.
In another aspect of the present invention, a method is provided for correlating an inline parameter to a device operation parameter of a device. Inline parameter data relating to a processed workpiece is received. The inline parameter data may include a shallow isolation trench critical dimension, a tunnel oxidation parameter, a source/drain critical dimension, a film stack measurement, a post etch critical dimension measurement, or a wafer electrical test parameter, all relating to the processed workpiece. A determination is made whether the inline parameter would result in a value of a device operation parameter within a predetermined range. At least one process operation performed upon the workpiece is adjusted in response to a determination that the inline parameter would not result in a value of the device operation parameter within a predetermined range.
In another aspect of the present invention, a method is provided for correlating an inline parameter to a device operation parameter of a device. Inline parameter data relating to a processed workpiece is received. The inline parameter data may include a shallow isolation trench critical dimension, a tunnel oxidation parameter, a source/drain critical dimension, a film stack measurement, a post etch critical dimension measurement, or a wafer electrical test parameter, all relating to the processed workpiece. A determination is made whether the inline parameter would result in an erase time value relating to a memory device that is within a predetermined range. At least one process operation performed upon the workpiece is adjusted in response to a determination that the inline p

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