Correlated double sampling circuit and CMOS image sensor...

Radiant energy – Photocells; circuits and apparatus – Photocell controlled circuit

Reexamination Certificate

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C348S241000

Reexamination Certificate

active

06977363

ABSTRACT:
A correlated double sampling circuit that reduces a shift in the potential of a node on the reference voltage side produced by reset operation. A reset signal RST is turned to “H” and then is turned to “L.” By doing so, a photodiode begins integration according to the intensity of light. This detected signal is sent to a CDS circuit. An SW1and a connection switch for sampling in the CDS circuit are turned to ON to accumulate the detected signal according to integration time in C1and C2as electric charges. After a certain period of time elapsed, the SW1and connection switch for sampling are turned to OFF to hold the detected signal sampled. Next, the RST is turned again to “H” and the SW1is turned to ON. Then the RST is turned to “L” and the SW1is turned to OFF. By doing so, reset noise is sampled and held in the C1. As a result, only a signal component can be extracted from the detected signal. After that a connection switch for outputting SW3and a connection switch for reading are turned to ON to transfer an output voltage signal according to the signal component included in the detected signal to an output bus line.

REFERENCES:
patent: 6326603 (2001-12-01), Kuderer

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