Correlated double sampler with single amplifier

Details Correlated double sampler with single amplifier Correlated double sampler with single amplifier

1999-01-19

2003-07-01

Garber, Wendy R. (Department: 2612)

Television

Camera, system and detail

Combined image signal generator and general image signal...

C348S243000

Reexamination Certificate

active

06587143

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to circuitry for preliminary processing of the raw output signal from a CCD image sensor. More particularly, the invention is (or includes) a correlated double sampler circuit including a single amplifier, having ping-pong architecture, and capable of processing a raw output signal from a CCD image sensor to generate an analog signal indicative of the value of each pixel of a sensed image.
2. Description of the Related Art
CCD (charge coupled device) image sensors are widely used to convert images into electronic signals that can be captured, transmitted, stored and displayed. Camcorders and digital still cameras typically use CCDs.
A CCD divides an image into a large number of discrete cells or pixels. The raw output signal produced by a CCD image sensor has a waveform of the type shown in FIG.
3
. The
FIG. 3
signal is a series of discrete analog voltage levels. The high voltage level (which immediately precedes the low level portion of each cycle) is commonly called the “reset level”, while the lower voltage level is commonly called the “signal level”, as indicated in FIG.
3
. The difference between a signal level and its preceding reset level indicates the amount of light (typically of a particular color) that has fallen on one particular pixel of the image sensor.
One characteristic of CCDs is that each reset level is slightly different from the others due to noise. For this reason, it is important to quantify the difference between the signal level and its preceding reset level; not the absolute value of the signal level. It is common practice in systems that use CCDs to employ a circuit called a correlated double sampler (CDS) to sample and hold the difference between these two voltage levels (for each pixel of the sensed image).
FIG. 1
is a simplified block diagram of a conventional circuit, which includes two CDS circuits (CDS
1
and CDS
2
) and has “ping-pong” architecture,” for preliminary processing of the raw output signal (labeled “IN”) of a CCD image sensor. The expression “ping-pong architecture” denotes that the
FIG. 1
circuit is configured and controlled to process consecutive samples (of the signal IN) at the rate of one sample per clock cycle, with CDS
2
processing every even sample and CDS
1
processing every odd sample. This architecture provides an efficient solution to the problem of how to accomplish three sequential functions (clamp, sample, and hold) in response to two clock edges only per clock cycle. Another advantage of this architecture is that the hold cycle during which amplifier PGA takes the difference between the reset level and signal level (of a single sampled pixel) and presents this difference as output signal OUT can be a full clock cycle long.
It is well known to implement correlated double samplers (CDS's). For example, the AD9801 integrated circuit product manufactured by Analog Devices, implements the
FIG. 1
circuit, which in turn includes two CDS's (CDS
1
and CDS
2
). This implementation of the
FIG. 1
circuit is described in C. Mangelsdorf, et al., “A CMOS Front-End for CCD Cameras,” Paper FA 11.5, Proceedings of the 1996 IEEE International Solid-State Circuits Conference (pp. 146-147 and 186-187).
In
FIG. 1
, CDS
1
includes circuitry implementing identical sample and hold circuits
1
and
2
and subtraction unit
5
, the circuits
1
and
2
being connected in parallel between the input node and subtraction unit
5
. CDS
2
includes circuitry implementing identical sample and hold circuits
3
and
4
(which are identical to circuits
1
and
2
) and subtraction unit
6
, the circuits
3
and
4
being connected in parallel between the input node and subtraction unit
6
. Each of circuits CDS
1
and CDS
2
is a sample and hold amplifier (which consumes power and has an offset value). Switch S
1
selectively passes the output of CDS
1
or CDS
2
to amplifier
7
, and the output of amplifier
7
is asserted to sample and hold circuit
8
. The amplified signal output from amplifier
7
(the “OUTPUT” signal) is typically asserted by circuit
8
to an analog-to-digital converter (not shown).
Elements
9
,
10
, and
13
(connected as shown) comprise a black level correction loop for CDS
1
, and elements
11
,
12
, and
14
(connected as shown) comprise a black level correction loop for CDS
2
. Each black level correction loop provides feedback to set the output voltage OUTPUT to a known value for CCD pixel outputs of zero value (black).
The difference between portions of the OUTPUT signal indicative of black pixels (i.e., corresponding to masked portions of the CCD sensor) which have been processed by CDS
1
, and a desired output signal, are integrated in integration circuit
9
. The output of circuit
9
is amplified in inverse amplifier
10
(whose gain is the inverse of amplifier
7
's gain) and fed back to one input of addition unit
13
, and unit
13
adds the output of amplifier
10
to the output of unit
5
being asserted to the other input of unit
13
. The difference between portions of the OUTPUT signal indicative of black pixels which have been processed by CDS
2
, and a desired output signal, are integrated in integration circuit
11
(which is identical to circuit
9
). The output of circuit
11
is amplified in inverse amplifier
12
(whose gain is the inverse of amplifier
7
's gain) and fed back to one input of addition unit
14
, and unit
14
adds the output of amplifier
10
to the output of unit
6
being asserted to the other input of unit
14
.
In each of correlated double samplers CDS
1
and CDS
2
, three functions must be executed during each clock cycle: sampling of the reset level, sampling of the signal level, and taking the difference between the two samples. The ping/pong approach, in which every odd sample of input signal IN (i.e., the first sample, the third sample, and so on) is processed by a first (ping) amplifier CDS
1
and every even sample is processed by a second (pong) amplifier CDS
2
, is an efficient solution to the problem of how to accomplish the three sequential functions in response to only two clock edges per amplifier per clock cycle.
Waveforms of the periodic control signals needed to operate the circuit of
FIG. 1
are shown in FIG.
1
A. On the falling edge of control signal Q
1
, CDS
1
samples the input signal IN and asserts this sample (which is the sampled reset level) to subtraction unit
5
. On the falling edge of control signal Q
2
, CDS
1
again samples the input signal IN and asserts this sample (which is the sampled signal level) to subtraction unit
5
, and a control signal (not shown) is asserted to switch S
1
to cause switch S
1
to couple the output of CDS
1
to amplifier
7
. Then, while switch remains in this state, CDS
2
samples the input signal IN on the falling edge of control signal Q
3
and asserts this sample (which is the sampled reset level for the next pixel) to subtraction unit
6
. Then, on the falling edge of control signal Q
4
, CDS
2
again samples the input signal IN and asserts this sample (which is the sampled signal level for the same pixel) to subtraction unit
6
, and another control signal (not shown) is asserted to switch S
1
to cause switch S
1
to couple the output of CDS
2
to amplifier
7
(thereby decoupling the output of CDS
1
from amplifier
7
). An advantage of the
FIG. 1
implementation is that the hold cycle during which each of amplifiers CDS
1
and CDS
2
takes the different between a reset level and a signal level and presents this difference as an output signal (through switch S
1
to amplifier
7
) is a full clock cycle in duration (such a full clock consists of a half cycle in which Q
1
is high and a half cycle in which Q
2
is high, or a half cycle in which Q
3
is high and a half cycle in which Q
4
is high).
A problem with the
FIG. 1
circuit is that each of sample and hold amplifiers CDS
1
and CDS
2
has its own offset voltage. Since each of CDS
1
and CDS
2
has a different offset voltage, two separat

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