Coded data generation or conversion – Converter calibration or testing
Reexamination Certificate
2003-02-21
2004-03-23
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
C341S118000, C341S155000
Reexamination Certificate
active
06710727
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a correction system of an A/D converter, and more particularly to a correction system of a Successive Approximation A/D Converter (SA-ADC).
2. Description of the Prior Art
The Successive Approximation A/D Converter (SA-ADC) of the prior art uses the dichotomy to find the corresponding digital value of the analog signal stage by stage. Basically, the outputting way of the SA-ADC is a series of outputting as well as outputting one bit per time from high bit to low bit. The converting rate of the SA-ADC is approximately 10 khz to 100 khz, and the resolution is approximately 10~16 bits.
Please refer to FIG.
1
.
FIG. 1
is a schematic diagram of the SA-ADC
10
in the prior art. The basic structure of the SA-ADC in the prior art comprises a comparator
12
, a register
14
, a D/A converter
16
, and a control unit
18
. The operation steps of the SA-ADC of the prior art are shown in the following. The first step, the middle value of the comparison range of the comparator
12
(e.g. the comparison range is 0~3V, and then the middle value is 1.5V) is converted to the highest bit of the SA-ADC
10
and buffered into the register
14
. Then, the register
14
inputs the value into the D/A converter
16
to convert to a middle voltage. The D/A converter
16
inputs the voltage into the comparator
12
to be a reference signal of the comparator and be compared with the level of the analog signal. If the level of the analog signal is higher than the middle voltage, the logic number [1] is output to represent the MSB of the analog signal. If the level of the analog signal is lower than the middle voltage, the logic number [0] is output to represent the MSB of the analog signal.
The second step, the result of the first step is input into the register
14
by the comparator
12
, and the register
14
feeds back the result to the D/A converter
16
to correct the reference signal of the comparator
12
before next comparison. The correction method is: If the first step outputs the logic number [1], the voltage, which is converted by the D/A converter
16
, will be the average value of the middle voltage of the SA-ADC and the upper bond of the comparison range (e.g. if the comparison range is 0~3V, the middle voltage is 1.5V, and the average value of the middle voltage and the upper bond is 2.25V), and the comparator
12
compares the voltage with the level of the analog signal. If the first step outputs the logic number [0], the voltage, which is converted by the D/A converter
16
, will be the average value of the middle voltage of the SA-ADC and the lower bond of the comparison range (e.g. if the comparison range is 0~3V, the middle voltage is 1.5V, and the average value of the middle voltage and the upper bond is 0.75V), and the comparator
12
compares the voltage with the level of the analog signal.
And so on, under the clock of the control unit
18
driving(one converting per clock), the SA-ADC changes the reference voltage continuously to compare with the analog signal until the converting of the LSB is finished. As the above, because every converting will reduce the comparison range to a half (the comparison range of the first step is 0~3V, and the comparison range of the second step is reduced to 1.5~3V or 0~1.5V), the output generated by the last converting will approach ±1 LSB of the analog signal. When every bit of the analog signal is confirmed, the converting result will be buffered into the register
14
and be the output of the SA-ADC
10
.
One factor of affecting the function of the SA-ADC is the D/A converter inside, because the Settling Time and Accuracy thereof limit the function of the SA-ADC. Due to the lack of the correction mechanism of the SA-ADC in the prior art, when the D/A converter does not have enough settling time or sufficient accuracy, the SA-ADC will output a result with an error. The sources of an error of the settling time and the accuracy may come from the devices mismatch or the overhigh converting rate of the SA-ADC. Therefore, the D/A converter cannot achieve the request of accuracy of ±½ LSB.
The devices mismatch cannot be corrected by a circuit but can be avoided by a circuit layout. The rate of the D/A converter can be improved by a circuit method, but more waste current and larger chip area are necessary. Therefore, if a correction mechanism is provided to the SA-ADC, one clock may be increased to make the D/A converter stably and reduce the request of subordinate circuit.
U.S. Pat. No. 4,620,179, the process of the SA-ADC is divided into two steps. The first step solves the front bit of the analog signal (CODE=X), and the second step uses the three voltage values corresponding to three front bits CODE=X+1, CODE=X, and CODE=X−1 as the reference signals of the comparator to compare with the analog signal and correct the front bit. In other words, this patent extends one unit from plus to minus for the comparison range corresponding to the front bit, which is solved by the first step, to achieve the objective of correcting the bit of the first step. For example, if the SA-ADC is 4 bits resolution, each of two steps solves 2 bits respectively. If the logic number solved by the first step is 10, at the second step, three voltage values of the logic numbers 11, 10, and 01 will be compared with the analog signal respectively to correct the result of the first step. By this method, the request of the settling time and the accuracy of the D/A converter in the first step is reduced. However, more delay time and more complex control logic are necessary than the prior art. The error cannot be corrected when the error occurs in the bit of the second step.
SUMMARY OF THE INVENTION
Accordingly, an objective of the present invention is to provide a correction system of a Successive Approximation Analog-to-Digital Converter (SA-ADC), which solves the problems generated by the prior art.
Another objective of the present invention is to provide a correction system of the SA-ADC, which has a simplified control logic and doesn't increase the delay time of the converter.
Another objective of the present invention is to provide a correction system of the SA-ADC, which can output complete and accurate digital data.
The present invention is a correction system of a Successive Approximation Analog-to-Digital Converter (SA-ADC). The converter is used for converting an analog signal to a digital data. The digital data is a series of N logic numbers D
i
(i=1~N) and has the same M logic numbers (D
N−M+1
~D
N
, 1≦M<N) in the last. The correction system is used for detecting if there is any error within the digital data after the digital data is generated, and correcting the digital data. The correction system comprises a detection module, a D/A converter, and a comparator for correcting the digital data under the following two conditions.
If the M logic numbers are the logic number [1]:
The detection module is used for proceeding the digital data and the logic number [1] with an addition operation to generate a first detection digital data. The D/A converter is used for receiving the first detection digital data and converting to a first detection signal correspondingly. The comparator is used for using the first detection signal as a reference signal of the comparator to compare with the analog signal. If the analog signal is higher than the first detection signal, the detection module outputs the first detection digital data to replace the digital data. If the analog signal is lower than the first detection signal, the detection module outputs the digital data.
If the M logic numbers are the logic number [0]:
The detection module uses the digital data to detect directly. The D/A converter is used for receiving the digital data and converting to a second detection signal correspondingly. The comparator is used for using the second
Mai Lam T.
Novatek Microelectronic Co.
Tokar Michael
Troxell Law Office PLLC
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