Correction static errors in a/d-converter

Details Correction static errors in a/d-converter Correction static errors in a/d-converter

2000-05-30

2001-05-08

Young, Brian (Department: 2819)

Coded data generation or conversion

Converter calibration or testing

C341S155000, C340S398100

Reexamination Certificate

active

06229467

ABSTRACT:

The present invention relates to correction of static errors in analog-to-digital converters using successive approximation procedures and to analog-to-digital converters, in particular to analog-to-digital converters having built-in error correction.
BACKGROUND
In wireless communication equipment incoming signals often have to be converted to a digital shape. Also, digital signals to be issued from the equipment often have to be converted to an analog shape. A schematic of a typical simple circuit used in such communication is illustrated in FIG.
1
. An analog-to-digital converter (ADC)
1
is connected to an incoming line
5
and delivers digital data to a signal processor
9
which communicates with user circuits, not shown, to forward information thereto. In actual embodiments the ADC has a transfer function which always includes errors. The errors result in a degraded performance in terms of signal-to-noise ratio (SNR) and spurious free dynamic range (SFDR). In a typical application, the incoming line
5
is connected to some device
8
for radio frequency receiving which receives signals from an antenna
10
.
Errors of one kind existing in the converting operation in an ADC are called static and are defined to be those errors which do not depend on the actual input signal to the ADC. These errors are approximately stable in time or change very slowly and will hereinafter be assumed to be permanent or constant in time. A typical example comprises matching properties.
The ADCs considered herein use a successive approximation procedure and are called SA-ADCs. Furthermore, they use binary search and subranging and in the subranging step redundant code is used, see Jan-Erik Eklund, “A/D conversion for sensor systems”, Thesis, Linköpings Universitet, 1998, Jiren Yuan, Christer Svensson, “A 10-bit 5-MS/s Successive Approximation ADC Cell Used in a 70-MS/s ADC Array in 1.2 &mgr;m CMOS”, IEEE Journal of Solid State Circuits, Vol. 29, No. 8, pp. 866-872, Aug. 1994, and “SPT7860, 10-BIT, 40 MSPS, 175 mW A/D CONVERTER”, Data sheet, Jul. 24, 1996, Signal Processing Technology, Inc., 4755 Forge Road, Colorado Springs, Colo. 80907, USA.
SUMMARY
It is an object of the invention to provide an efficient digital error correction of an ADC, in particular of a parallel ADC, using no special trimming signals.
It is another object to provide methods and devices for correcting static mismatches in ADCs.
Thus a method of correcting, in the digital domain, static, in particular matching, errors in the analog domain is provided. In the method the following steps can be executed:
1. Measuring the actual histogram of the uncorrected digital values output from the ADC.
2. Estimating an expected histogram from the measured histogram.
3. Calculating the deviation of the measured histogram from the expected histogram.
4. Calculating a correction table based on the calculated deviation.
5. Correction output data by using values from the correction table to correct uncorrected data, e.g. adding the value to an uncorrected digital value.
Also, gain and offset errors in ADC cells in parallel ADCs can be corrected. An ADC is provided which has a reference level generator which gives a good stability of the generated coarse reference levels but still not requires too many components to provide the fine reference levels.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the methods, processes, instrumentalities and combinations particularly pointed out in the appended claims.


REFERENCES:
patent: 4736189 (1988-04-01), Katsumata et al.
patent: 5777569 (1998-07-01), Naruki et al.

Affiliated with

Also associated with

Rating

Correction static errors in a/d-converter does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Correction static errors in a/d-converter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Correction static errors in a/d-converter will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2465207