Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2000-12-22
2003-07-01
Pert, Evan (Department: 2829)
Semiconductor device manufacturing: process
With measuring or testing
C702S083000
Reexamination Certificate
active
06586263
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the manufacturing of integrated circuits. More specifically, the present invention relates to identifying defects in integrated circuits being manufactured on a wafer.
PRIOR ART
Integrated circuits are commonly manufactured in batches on wafers. Multiple integrated circuits are manufactured on a single silicon wafer during the manufacturing process. Referring now to
FIG. 1
, there is shown a silicon wafer having a plurality of integrated circuits disposed thereon referenced by numbers
12
,
14
,
16
, and
18
.
During the manufacturing process, multiple masking processes are performed on the semiconductor wafer. Each masking process defines where features on various layers that make up the integrated circuit are to be positioned. For example, a layer of polycrystalline silicon may be deposited on a wafer. Then photosensitive resist is coated on the wafer and selectively exposed to light so that after developing the resist, the remaining resist forms a pattern. This pattern is then transferred to the polysilicon during an etch step so that after the remaining resist is removed, the polycrystalline silicon forms a pattern defined by the selective light exposure.
This masking and etching process sequence is repeatedly carried out on each wafer to create the intricate interconnected patterns of semiconductors, insulators, and metals needed to create the desired integrated circuit (IC).
The process described above is carried out to produce a plurality of IC's on a wafer as shown in FIG.
1
. For example, a single silicon wafer may be the basis for tens to thousands of IC's. The ability to manufacture a plurality of IC's on a single silicon wafer reduces the overall cost of production, thereby passing these cost savings onto the consumer in the form of inexpensive IC's.
With advancements in technology, IC's have become very small and very complex. With each generation, IC features become smaller because of advancements in the manufacturing process described above. However, with these advancements it has become more difficult to detect defects.
As part of the manufacturing process, in an effort to reduce the number of defective IC dice, it is common to inspect all of, or a sample of, the dice on a sampling of the wafers being produced. The inspection may be an optical inspection with very sensitive optical instruments capable of detecting defects of the size of a minimum feature of the IC or might be an electrical test that, in the case of memories, is capable of locating the position of an electrical defect to within the area of one small cell. The artifacts that are detected serve to guide the engineers to where defects, which may lead to yield loss, occur.
Referring now to
FIG. 1
there is shown a wafer having four dice labeled
12
,
14
,
16
, and
18
. The labeled dice illustrate how a wafer may be inspected during manufacturing. For example, each of these dice, either picked randomly or according to some reason, would be inspected for defects.
Referring now to
FIG. 2
, there is shown a hypothetical collection defects that might be observed in an inspection report generated from inspecting the dice shown in
FIG. 1. A
line defect
24
is illustrated on die in
FIG. 2. A
line defect may be caused by a scratch on the wafer. Also shown on dice
12
,
14
, and
16
in
FIG. 2
, are a plurality of “point” defects
22
,
26
,
28
,
34
,
36
, and
38
. Also illustrated on die
16
in
FIG. 2
is a large continuous defect
30
and a cluster of point defects
32
on die
18
.
Referring now to prior art
FIG. 3
, there are shown defects
42
,
44
,
45
,
46
,
48
,
52
,
54
,
58
,
60
,
62
, and
68
that might be observed on another inspection report of the same dice later in the manufacturing process. The outline of the die is shown for illustrative purposes only in
FIGS. 2 and 3
and would not be generally available in a standard defect inspection report.
Defects that occur on one layer may propagate through and also appear on subsequent levels during the manufacturing and inspection process. For example, a large contaminating particle that remains after cleaning of the polysilicon layer, might penetrate through the intervening dielectric layer and be seen on the metal contact layer. It is important to identify these propagating defects so that the cause of the defects can be correctly assigned.
After locating the defects, an overlay report may be generated in which the defects from the inspections of the successive layers are displayed together with the intention of identifying those defects that are reported to be at the same location on inspection of successive layers. However, experience has shown that there is an offset in the reported origin of the inspections between layers.
Referring now to
FIG. 4
, there is shown an exemplary overlay report as would be created after performing at least two inspections. As shown in
FIG. 4
, an offset in the origins of the coordinate systems used to report the location of the defects may cause the defects from one layer to be incorrectly positioned with respect to those defects of a second layer. This offset has been a recurring problem in the manufacture of integrated circuits and, as the size of the integrated circuits features are reduced and the number of dice on a wafer increases, there is a growing need to correct this problem.
Thus, when an overlay inspection report is generated as shown in
FIG. 4
, propagating defects may not be identified. As shown in
FIG. 4
, only individual point defects from the defect clusters
32
and
62
would be selected. An attempt to identify correlated defects as those lying within some critical distance of each other would mistakenly select the pair of defects
48
, both of which come from the second inspection. A more sophisticated correlation algorithm based on defects from successive inspections that lie within a critical distance would misidentify defects
45
and
26
as being correlated when in fact they are not.
Therefore, there is a need for a procedure for automatically detecting the origin offset between the inspections and correcting the offset in the overlay report so that the correlated defects that propagate between layers can be identified correctly. The present invention provides a method and apparatus for correcting these.
It is an object of the present invention to provide methods for correcting the offset between origins of coordinate systems for layers so that during the manufacturing process correlating defects are correctly identified. It is a further object of the present invention to provide a method that can be implemented during the manufacturing process so that defective dice can be disposed of properly.
SUMMARY OF THE INVENTION
The present invention provides a method for detecting correlated defects during the manufacture of integrated circuits. In one embodiment, the method of the present invention searches for pairs of defects lying within a given distance of each other from differing layers. The distances or spacings between pairs are calculated and a statistical algorithm is performed to determine if the defect pair spacings are distributed randomly. If there exists a subset of defect pairs is isolated and used to calculate the offset of the origins of the coordinates of each of the layers.
In a second embodiment, the method of the present invention automatically searches for defect pairs between layers over a space equal to the size of the die being inspected using a k-restricted sampling where k is restricted to a small integer, typically k ranges from 0 to 3. The use of k-restricted sampling ensures that problems caused by clustered defects are avoided. Once the defect pairs are selected by either of the methods described above, the defect pairs are tested to determine whether the spacing between the members of the pairs are distributed randomly. If the distribution is not random, the non-random subset of defect pairs is isolated, then the isolated subset of defect pairs is u
Muradian David
Sagatelian Arman
Neuristics Physics Laboratory, Inc.
Pert Evan
Sierra Patent Group Ltd.
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