Coded data generation or conversion – Converter compensation
Reexamination Certificate
2001-05-02
2002-12-31
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Converter compensation
C341S120000, C341S143000, C341S155000, C341S156000
Reexamination Certificate
active
06501400
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
N/A
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
N/A
BACKGROUND OF THE INVENTION
Pipelined analog-to-digital converters (ADCs) are well known in the art. A typical pipelined ADC includes a plurality of ADC stages in which each ADC stage converts a portion of an analog input signal into one or more digital bits. The first ADC stage receives the analog input signal and provides two outputs, the first output includes one or more digital bits and the second output is an analog residue voltage. The one or more digital bits represent the portion of the analog input signal that has been converted into a digital format. The analog residue voltage represents the amount of the analog input signal remaining after the portion converted into the one or more digital bits by the ADC stage has been removed. Each subsequent ADC stage receives the analog residue voltage from the preceding ADC stage and converts a portion of it into one or more digital bits. The ADC stage then removes that portion converted into the digital format from the received input analog residue signal and provides an output analog residue signal to the next adjacent stage. Typically, the first ADC stage in a pipelined ADC provides the most significant bit(s) and the last stage provides the least significant bit(s). The digital bits from each ADC stage taken together represent the digital value of the input signal provided to the ADC.
FIG. 1
illustrates a typical prior art pipeline ADC
100
having a main pipeline
101
that includes a plurality of N stages
102
,
104
,
106
,
108
, and
110
. The first stage
102
receives an input signal, Vin, on input line
111
. Each stage
102
-
110
provides one or more digital output bits on lines
103
-
111
respectively. Stage
108
is shown in more detail as an exemplary ADC stage.
Stage
108
includes a M-bit ADC
112
that receives the input signal V
in
via line
109
. The input signal V
in
may be either the analog input signal or a residue signal from a preceding stage. The M-bit ADC
112
provides M-bits as an output digital signal on line
114
. A M-bit digital-to-analog-converter
116
also reads the M-bit digital output and provides an analog voltage on line
117
that corresponds to the M-bit word provided by ADC
112
. A subtraction module
119
subtracts the analog voltage on line
118
from the input voltage V
in
on line
109
. The resulting difference is the residue of the input signal remaining after the portion of the input voltage converted by the ADC stage
112
has been removed. An amplifier
120
amplifies the residue voltage, wherein the amplifier has a gain equal to 2
M
, or in some cases 2
M−1
. The amplified residue signal is provided to the next adjacent ADC stage in the pipeline via line
122
.
In theory the pipelined ADC
100
should provide a nearly perfect digital representation of the input signal. However, in practice the components and amplifiers used in the pipelined ADC are not ideal. For example the operational amplifiers (op-amps) used in the amplifier modules in each ADC stage have a finite open-loop gain. Because of the finite gain, each amplifier module has a gain that is not 2
M
. Therefore, the residue signal provided by the amplifier will not accurately reflect the amount of the analog signal after the digitized portion has been removed therefrom. In addition to amplifying and promulgating the errors form preceding stages, each stage will also add a finite gain error to the overall error that will be further amplified by the down-stream amplifiers in the main pipeline as well.
FIG. 2
is a typical op-amp circuit configured and arranged to function as the amplifier
120
depicted in FIG.
1
. The gain of the amplifier is given by:
V
out
=
V
in
*
G
1
+
G
A
⇒
V
out
≈
V
in
*
G
(
1
-
G
A
)
(
1
)
Where the nominal gain of the amplifier, G, is equal to (C1+C2)/C
2
. As illustrated by equation (1) however the error term G/A reduces the actual gain of the amplifier. If the open-loop gain, A, is not large enough such that this error term is insignificant, then the actual gain of the amplifier stage will be smaller than expected. Consequently, the residue signal will be smaller than anticipated and each subsequent analog to digital conversion of the residue signal will result in an inaccurate output. As noted above, this inaccurate output will be amplified and promulgated by each subsequent ADC stage. Each ADC stage will also add to the overall error due to the finite gain errors inherent in each of the amplifier modules comprising the ADC stages. Therefore, as the residue signal propagates from stage to stage, the error from the upstream ADC stages is amplified and added to by each downstream ADC stage. Because of the size constraints and the processing required when making a pipelined ADC, the open loop gains of the op-amps often have a value of one-thousand (1000) or less and therefore the finite gain errors cannot be ignored.
Therefore it would be advantageous to provide a pipelined ADC that has reduced errors caused by the finite gain of the operational amplifiers used within the amplifier modules of the pipelined ADC.
BRIEF SUMMARY OF THE INVENTION
A pipeline analog to digital converter that includes a main pipeline including a plurality of analog to digital converter stages and a shadow pipeline for compensating the output of the main pipeline. Each of the analog to digital converter stages in the main pipeline provides a digital output and an analog residue signal. The shadow pipeline includes one or more stages that receive at least one gain error signal from one of the analog to digital converter stages in the main pipeline. The shadow pipeline is configured and arranged to processes the gain error signal to form a compensation signal. The compensation signal is combined with the analog residue signal to provide a compensated residue signal in which the finite error gain has been substantially removed. Alternatively, the compensation signal may be converted into a digital format and combined with the digital output bits of one or more of the analog to digital converter stages in the main pipeline to provide a compensated digital output that has had substantially all of the gain error removed therefrom.
In one embodiment, a plurality of analog to digital converter stages in the main pipeline form a plurality of error correcting stages that provide one or more gain error signals to the shadow pipeline. The shadow pipeline processes the received gain error signals and provides a compensation signal. The compensation signal is combined with the analog residue signal to provide an input to a subsequent stage that is substantially free of finite gain error from the preceding amplifier stages.
In another embodiment, the shadow pipeline receives a plurality of gain error signals from a plurality of analog to digital converter stages and accumulates and processes these gain error signals to provide a compensation signal. The compensation signal may be combined with a corresponding analog residue signal to remove the finite gain error terms, or the compensation signal may be converted into a digital form and combined with the digital bits provided as outputs from one or more of the analog to digital converter stages in the main pipeline to remove the finite gain errors contained therein.
REFERENCES:
patent: 6037891 (2000-03-01), Griph
Brady W. James
Nguyen Linh Van
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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