Correction of DC offset in data bus structures at the receiver

Details Correction of DC offset in data bus structures at the receiver Correction of DC offset in data bus structures at the receiver

2000-05-11

2002-03-12

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Converter calibration or testing

C341S144000

Reexamination Certificate

active

06356218

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
Aspects of the invention relate to parallel data bus structures. Other aspects of the present invention relate to the detection and correction of DC offset incorporated in a digital data signal as it is transmitted over a parallel data bus.
2. Description of Related Art
In a computer environment, a parallel data bus typically provides the main communication link between CPUs and peripheral devices such as disk drives, printers, scanners, and any other device requiring access to the bus for transmitting and receiving information. The maximum length of the bus as well as the maximum number of peripheral devices that can be connected to the bus is dictated by a protocol that corresponds to the type of bus used. In addition to these parameters, the protocol also specifies the maximum rate at which data can be transmitted across the bus.
One such parallel data bus is the Small Computer System Interface (SCSI). SCSI is a set of ever changing electronic interface standards/protocols that allow faster and more flexible parallel communication between computers and peripheral hardware over previous interfaces. For example, the Ultra-3 SCSI standard/protocol specifies a bus that can be 12 meters in length, connect up to 16 devices, and transmit data at a rate of 160 Mbytes per second (40 MHz). A list of the various adopted SCSI standards/protocols and their main attributes are summarized in TABLE 1.
TABLE 1
Maximum
Maximum
Maximum
Cable
Maximum
Number
SCSI Standard
Length (m)
(M bytes/sec)
of Devices
SCSI-1
6
 5
 8
SCSI-2
6
 5-10
8 or 16
Fast SCSI-2
3
10-20
 8
Wide SCSI-2
3
20
16
Fast Wide SCSI-2
3
20
16
Ultra SCSI-3, 8-bit
1.5
20
 8
Ultra SCSI-3, 16-bit
1.5
40
16
Ultra-2 SCSI
12
40
 8
Wide Ultra-2 SCSI
12
80
16
Ultra-3 (Ultra 16O/m) SCSI
12
160 
16
The SCSI standard is subject to the same signal distortion and interference that is seen in most digital transmission devices. Examples of interference that affect communications between devices on a SCSI parallel data bus include inter-symbol interference (ISI), noise coupled to the transmission line from external sources, and DC offset, which is the phenomenon of a DC voltage being added to a transmitted signal either by the transmitter or by the signal path. This interference can result in the unreliable detection of data by a receiver.
When data transmission speeds are increased, the frequency content is also increased. When a signal with a high data rate is transmitted over a finite bandwidth medium, its amplitude is attenuated. As an example, consider a non-return to zero (NRZ) SCSI signal propagating at 80 MHz (320 Mbytes/s) over a distance of ten meters. Attenuation of this signal can reach up to twelve decibels; i.e., only ¼ of the amplitude of the original signal reaches its destination.
In a SCSI environment, the transmitted signal faces random DC offsets estimated at±100 mV. While the amplitude of the signal is attenuated, the DC offsets are not, and they represent a significant portion of the received signal. As a consequence, erroneous bit detection may occur at the receiver. If the original amplitude of the signal in the above example is 500 mV and the transmitter introduces a 50 mV DC offset, this only results in a 10% error. However, this same signal at the receiver after traversing the SCSI data bus and experiencing a 12 decibel attenuation has an amplitude of 125 mV. Now, the 50 mV DC offset constitutes a 40% error.
FIG.
1
A and
FIG. 1B
illustrate the concept of DC offsets.
FIG. 1A
shows a graph of two signals, [ap sin(&ohgr;t)+dp]
104
and [am sin((&ohgr;t)+dm]
106
, that comprise a differential signal [ap sin(&ohgr;t)+dp−(am sin(&ohgr;t)+dm)]
102
, where dp and dm are the DC offsets associated with each signal. As is shown, dp=dm=0 in
FIG. 1A
; hence the DC offset is zero. In
FIG. 1B
, the signals
102
,
104
and
106
are shown with a DC offset introduced. When signals
104
and
106
are combined to produce the differential signal
102
, the DC offset represents 12.5% of the peak-to-peak amplitude, as is shown. If this signal suffers 12 decibels of attenuation during transmission, the DC offset will prevent the receiver comparator from switching during transitions, as there is sufficient DC offset for the single ended signals never to cross each other, i.e., the transmitted information can not be detected and is lost.
The low voltage differential (LVD) signaling scheme currently used to detect SCSI signals compensates for dc offset introduced by terminator circuits to ensure deassertion on a floating or idle bus. However, this compensation technique does not sense and correct actual signal path offset.
Therefore, a need exists for a novel/improved apparatus and method that will mitigate the DC offset that an information signal experiences as a result of its transmission across a parallel data bus (e.g., a SCSI parallel data bus) between devices.


REFERENCES:
patent: 4143361 (1979-03-01), Tammes et al.
patent: 4542354 (1985-09-01), Robinton et al.
patent: 5877645 (1999-03-01), Comine et al.
patent: 5898395 (1999-04-01), Werrbach et al.

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