Correction method leading to a uniform threshold voltage distrib

Static information storage and retrieval – Floating gate – Particular biasing

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36518529, 36518533, 365218, G11C 1300

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active

056086725

ABSTRACT:
A method for correcting over-corrected memory cells in a flash EPROM. The flash EPROM includes an array of memory cells (25), where each of the cells includes a gate 18, a floating gate (16), a source (12), a drain (14), and a substrate (10). The method includes bulk erasing each of cells in the array of cells (step 40), which results in a plurality of over-erased cells. The over-erased cells are then corrected (step 42), which results in a plurality of over-corrected cells. The over-corrected cells are identified (step 44) and selectively erased (step 46), such that a uniform threshold voltage distribution (54) is provided for the cells in the flash EPROM.

REFERENCES:
patent: 5357463 (1994-10-01), Kinney
patent: 5406521 (1995-04-01), Hara
patent: 5416738 (1995-05-01), Shrivastava
patent: 5424993 (1995-06-01), Lee et al.

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