Miscellaneous active electrical nonlinear devices – circuits – and – External effect – Temperature
Reexamination Certificate
2003-05-28
2004-11-23
Nguyen, Minh (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
External effect
Temperature
C327S262000, C326S032000
Reexamination Certificate
active
06822504
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a correction circuit for generating a control signal for correcting a characteristic change caused by production conditions or physical conditions such as power supply and temperature in a transistor included in a semiconductor integrated circuit; and a delay circuit and a ring oscillator circuit including such a correction circuit. In particular, the present invention relates to a correction circuit, a delay circuit and a ring oscillator circuit which can be preferably used for, for example, generating a reference clock generation circuit (timing generation circuit) in, for example, an internal synchronization semiconductor memory device.
2. Description of the Related Art
Some delay circuits used as a timing generation circuit or the like in a CMOS semiconductor integrated circuit use a CMOS transistor. A delay circuit using a CMOS transistor uses signal transmission delay characteristics of the transistor which are determined by, for example, the driving load, the ON resistance, and the driving current of the transistor.
FIG. 6
shows a conventional delay circuit
100
using signal transmission delay characteristics of a transistor.
The delay circuit
100
includes a plurality of inverter circuits
103
connected to each other in series. In each inverter circuit
103
, a p-channel (hereinafter, referred to as “Pch”) transistor
101
and an n-channel (hereinafter, referred to as “Nch”) transistor
102
are complementarily connected to each other as a pair between a supply terminal (supply voltage) and a ground terminal (ground voltage: earth). A gate of the Pch transistor
101
and a gate of the Nch transistor
102
included in each inverter circuit
103
each receive a signal from an input terminal or a signal from the previous-stage inverter circuit
103
. A connection point between the Pch transistor
101
and the Nch transistor
102
outputs a signal to the subsequent-stage inverter circuit
103
or an output terminal.
When, for example, a signal from the input terminal or the previous-stage inverter circuit
103
is at an H level (supply voltage level), the Pch transistor
101
is turned OFF (non-conductive state) and the Nch transistor
102
is turned ON (conductive state). Therefore, the connection point between the Pch transistor
101
and the Nch transistor
102
outputs a signal at an L level (ground voltage level) to the subsequent-stage inverter circuit
103
or the output terminal. When a signal from the input terminal or the previous-stage inverter circuit
103
is at an L level, the Pch transistor
101
is turned ON and the Nch transistor
102
is turned OFF. Therefore, the connection point between the Pch transistor
101
and the Nch transistor
102
outputs a signal at an H level to the subsequent-stage inverter circuit
103
or the output terminal.
A delay time in the delay circuit
100
having the above-described structure will be described. A delay time is defined in a delay circuit as a time period from when an input signal voltage reaches the prescribed voltage until an output signal voltage reaches a prescribed voltage.
FIG. 7
is a timing diagram illustrating the timing of an input signal voltage and an output signal voltage in the delay circuit
100
. In
FIG. 7
, the supply voltage is labeled as “VCC”, and the ground voltage is labeled as “GND”. Here, the delay time is a time period in the delay circuit
100
from when the input signal voltage becomes ½ VCC until when the output signal voltage becomes ½ VCC.
The delay time in the delay circuit
100
greatly changes in accordance with the characteristics of the transistors (driving current, threshold level, etc.) included in the delay circuit. In general, the transistor characteristics are dispersed by, for example, supply voltage used for the delay circuit, ambient temperature of the delay circuit, and the production parameters of the delay circuit such as gate thickness, gate width, gate length and the like.
Thus, in the delay circuit
100
including the inverter circuit
103
shown in
FIG. 6
having a simple structure, the delay time shown in
FIG. 7
is dispersed by the supply voltage, ambient temperature, production parameters, and the like. A change in delay time caused by the dispersion does not necessarily have favorable results on the other circuits included in the semiconductor integrated circuit. For example, when a set delay time is set under certain conditions, the delay time may be too long or too short under other conditions.
Japanese Laid-Open Publication No. 7-38394 proposes a circuit for controlling the delay time.
FIG. 8
shows a conventional delay circuit
200
including a first correction circuit
210
and a second correction circuit
220
for controlling the delay time.
The delay circuit
200
includes a plurality of inverter circuits
205
a
and a plurality of inverter circuits
205
b
alternately connected in series. In the example of
FIG. 8
, a total of four inverter circuits (two inverter circuits
205
a
and two inverter circuits
205
b
) are provided. Each inverter circuit
205
a
includes a logic inversion circuit
203
which includes a Pch transistor
201
and an Nch transistor
202
complementarily connected as a pair, and a Pch transistor
204
a
connected in series between the logic inversion circuit
203
and the supply terminal. Each inverter circuit
205
b
includes a logic inversion circuit
203
which includes a Pch transistor
201
and an Nch transistor
202
complementarily connected as a pair, and an Nch transistor
204
b
connected in series between the logic inversion circuit
203
and the ground terminal.
A gate of the Pch transistor
201
and a gate of the Nch transistor
202
included in each logic inversion circuit
203
each receive a signal from an input terminal or a signal from the previous-stage logic inversion circuit
203
. A connection point between the Pch transistor
201
and the Nch transistor
202
outputs a signal to the subsequent-stage logic inversion circuit
203
or an output terminal.
A gate electrode of the Pch transistor
204
a
included in the inverter circuit
205
a
receives a voltage (control signal) generated in the first correction circuit
210
. A gate electrode of the Nch transistor
204
b
included in the inverter circuit
205
b
receives a voltage (control signal) generated in the second correction circuit
220
.
In the delay circuit
200
, the driving capability of each transistor or the like is adjusted such that the delay time is dominantly controlled by the Pch transistor
204
a
and the Nch transistor
204
b
. Thus, the delay time can be controlled in accordance with the characteristics of output voltages (control signals) of the first correction circuit
210
and the second correction circuit
220
. As a result, the delay time caused by the delay circuit
200
can be substantially the same regardless of the conditions.
FIG. 9A
is an equivalent circuit of an operation of the first correction circuit
210
shown in Japanese Laid-Open Publication No. 7-38394, and
FIG. 9B
is an equivalent circuit of an operation of the second correction circuit
220
also shown in Japanese Laid-Open Publication No. 7-38394.
The first correction circuit
210
includes a Pch transistor
301
and a resistor
302
connected in series in this order between the supply terminal and the ground terminal. A gate electrode of the Pch transistor
301
is connected to the ground voltage. A connection point (PO node) between the Pch transistor
301
and the resistor
302
outputs a voltage (control signal) PO. The second correction circuit
220
includes a resistor
304
and an Nch transistor
303
connected in series in this order between the supply terminal and the ground terminal. A connection point (NO node) between the resistor
304
and the Nch transistor
303
outputs a voltage (control signal) NO.
An operation of the first correction circuit
210
and the second correction circuit
220
having the above-described structure will be described.
Nguyen Minh
Sharp Kabushiki Kaisha
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