Correction and monitoring of transient errors in a memory system

Details Correction and monitoring of transient errors in a memory system Correction and monitoring of transient errors in a memory system

1983-03-11

1985-08-13

Atkinson, Charles E.

Excavating

371 38, G06F 1110, G11C 2900

Patent

active

045354553

ABSTRACT:
A microcomputer system in which transient errors occurring in a memory are corrected and logged by a program controlled microprocessor and a simple error detection and correction circuit. When an error occurs in information readout of a memory location, the error detection and correction circuit is responsive to the error to (1) store the address of memory block containing the location, (2) store the type of error, and (3) generate an error signal which interrupts the microprocessor. In response to the interrupt, the microprocessor enters an interrupt routine to: (1) identify the block of memory locations in which the error occurred, (2) determine the type of error, (3) reaccess each memory location of the memory block to effect a rereading thereof, (4) receive each word of readout information, corrected if necessary by the error detection and correction circuit, (5) rewrite each of the received words back into the memory at the proper reaccessed memory location, (6) read out each of the rewritten locations to determine if any error is still present which would indicate a permanent rather than a transient error, and (7) finally, log the error in an error rate table if it is a transient error.

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"Dynamic-RAM Controller Times, Refreshes, Arbitrates, and Scrubs", Electronics, May 5, 1982, pp. 172, 174.

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