Correcting for DC offset in a phase locked loop

Details Correcting for DC offset in a phase locked loop Correcting for DC offset in a phase locked loop

2006-05-09

2006-05-09

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By shape

C327S156000, C327S163000

Reexamination Certificate

active

07042252

ABSTRACT:
A technique for correcting for DC offset in a phase locked loop involves generating digital phase information in response to an input signal and then generating an offset correction signal in response to the digital phase information. The digital phase information may include transition samples that are integrated to generate the offset correction signal. Integrating the transition samples helps to compensate for the effects of phase noise, especially phase noise that is contributed by the input signal and/or the recovered clock signal.

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