Coreless substrate and manufacturing thereof

Details Coreless substrate and manufacturing thereof Coreless substrate and manufacturing thereof

2007-02-15

2009-10-20

Williams, Alexander O (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257SE23085, C257SE23004, C257S678000, C257S777000, C257S778000, C257S723000, C257S784000, C257S786000, C257S737000, C257S738000, C257SE25023

Reexamination Certificate

active

07605459

ABSTRACT:
An aspect of the present invention features a manufacturing method of a package on package with a cavity. The method can comprise (a) forming a first upper substrate cavity in one side of an upper substrate; (b) mounting an upper semiconductor chip on the other side of the upper substrate; (c) forming a lower substrate cavity in one side of a lower substrate; (d) mounting a lower semiconductor chip in the lower substrate cavity formed in the lower substrate; and (e) stacking the upper substrate above the lower substrate such that the first upper substrate cavity accommodates a part of the lower semiconductor chip. The package on package and a manufacturing method thereof can reduce the overall thickness of the package by forming cavities in both upper and lower substrates to accommodate a semiconductor chip mounted in the lower substrate.

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Korean Patent Office Action, mailed Oct. 26, 2007 and issued in Korean Patent Application No. 10-2006-0014917.
Chinese Patent Office Action, mailed Mar. 21, 2008 and issued in corresponding Chinese Patent Application No. 200710079522.5.

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