Communications: electrical – Digital comparator systems
Patent
1974-02-19
1976-09-21
Urynowicz, Jr., Stanley M.
Communications: electrical
Digital comparator systems
340174CR, 340174M, 340174DA, 340174AC, G11C 702, G11C 1106
Patent
active
039822338
ABSTRACT:
A three wire 3D core memory which utilizes the same balanced pairs of sense-inhibit conductors to conduct both high energy common mode inhibit currents and low energy differential mode core switching signals includes pairs of antiparallel Schottky diodes interconnecting the conductor pairs at symmetrical positions therealong intermediate the cores of each memory mat. As high energy common mode inhibit currents are generated small deviations from perfect symmetry of electrical characteristics along the sense-inhibit conductors results in the appearance of differential voltages which are substantial in comparison to switching signal voltages. The sense-inhibit recovery time required for dissipation of these spurious differential voltage signals before a memory read cycle can proceed consumes a substantial portion of a memory cycle for large stacks. The Schottky diodes substantially reduce this recovery time to greatly improve memory cycle time by limiting the differential voltages to the low threshold forward conduction voltage thereof and by appearing as transmission line discontinuities to break up differential voltage signals which remain after termination of an inhibit current into higher frequency harmonic components which are more rapidly attenuated. The Schottky diodes have no substantial effect upon the sensed output switching signals because the threshold forward bias voltage of the Schottky diodes is greater than the peak switching signal voltage.
REFERENCES:
patent: 3548391 (1970-12-01), Perlman
patent: 3675224 (1972-07-01), Ninomiya et al.
patent: 3774181 (1973-11-01), Wells et al.
patent: 3824569 (1974-07-01), Schuur
Ampex Corporation
Urynowicz, Jr. Stanley M.
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